Accelerate Design Signoff with the Updated Cadence Voltus Training Kit
By Ronen Stilkol, Senior AE Architect As advanced-node and 3D-IC designs push higher performance into tighter power, thermal, and packaging constraints, engineers must understand how the die, package,...
View ArticleCadence Welcomes Xinqiao Electronics to the Certified Training Partner Program
The semiconductor industry requires a highly skilled workforce and demands that recent engineering graduates swiftly bridge the gap between academia and practical application. This is where the Cadence...
View ArticlePSS 3.1 Channels: The Game Changer for Target-Time Communication
Portable Stimulus models already feature powerful language constructs to describe scenario intent. Activities, constraints, resources, buffers, streams, and states let the Perspec solver build a legal...
View ArticleSmart Corners Analysis Helps You Focus on the Conditions That Matter the Most!
Imagine you are designing a precision analog block targeted for a high‑volume product. Your schematic looks clean, specifications pass across nominal conditions, and traditional PVT corners seem well...
View ArticleThe Three Phases of AI Adoption
Artificial intelligence is often discussed as if the industry is moving through a single technology cycle. But AI adoption is not unfolding as a single event; it is unfolding in waves. The first phase...
View ArticleThe Three-Layer Cake: The Foundation Behind Intelligent Engineering
Artificial intelligence is rapidly becoming the engine behind the next era of technology innovation. From hyperscale data centers and autonomous systems to robotics and scientific discovery, AI is...
View ArticleDesign for AI and AI for Design
The semiconductor industry is experiencing a once-in-a-generation transformation. Recent projections suggest the semiconductor market could approach $2 trillion by 2030 , driven by the rapid rise of AI...
View ArticleAI Infrastructure Starts Beyond the Chip
Why Advanced Packaging and PCB Design Have Become the Next Frontier of Innovation For much of the AI revolution, competitive advantage has been measured by one metric: building faster chips. Every...
View ArticleThe Top Five Reasons to Use Cradle CFD 2026.1
If you’ve been weighing whether it’s time to upgrade your CFD software , Cradle CFD 2026.1 makes a very strong case for taking the time and effort to update. This release introduces new physics, new...
View ArticleCadence RTL Design Studio: Built for the Full PPAC Journey
If you've used Joules RTL Design Studio, you already know what it can do. Now it has a name that matches its full potential. We're renaming Joules RTL Design Studio to Cadence RTL Design Studio . The...
View ArticleThe Truth About Complete DFT Flow: What Most Engineers Miss
Design for Testability is a critical step in achieving high-quality silicon. In this Training Bytes blog, we are going to explore implementing an efficient DFT flow using the Genus Synthesis Solution,...
View ArticleWhy 10BASE-T1S Automotive Ethernet SoC Verification Needs More Than Simulation?
Cadence Multi-Platform Verification improves functional coverage and verification time The recent advancements in the automotive industry, such as ADAS/AV, and infotainment all depend on reliable...
View ArticleHow the New ASK AI Assistant Makes Support More Seamless
Finding the right answer often takes more than one question. Users may start with a broad query, add details, clarify the issue, or ask a related follow-up before reaching what they need. The new ASK...
View ArticleHow Fidelity CFD Improves Hydraulic Turbine Performance Prediction
Francis-99 Hydraulic Turbine (Trivedi, 2026) Accurately predicting the performance of hydraulic turbines requires more than a steady-state efficiency estimate. Engineers also need insight into how the...
View ArticleYou'll Still Do the Work—You Just Won't Do the Boring Part
Agentic AI is about to change your flow. Here's what actually shifts—and why the engineers who move first will pull away from the ones who wait. It's 11 p.m. The overnight regression failed—again—and...
View ArticleUnderstanding PCIe 6.0 Power States: L0p vs L0s vs L1
PCI Express has always focused on a single goal: maximizing performance while minimizing power. However, with PCIe 6.0, maintaining this balance has become far more challenging. With PAM4 signaling in...
View ArticleHow Cadence and TSMC Are Accelerating AI Silicon Design at Advanced Nodes
Designing AI silicon for increasing AI/HPC workloads at advanced nodes has become one of the toughest challenges in the semiconductor industry. Escalating goal-driven PPA, reliability, and...
View ArticleEverything to Look Forward to in Actran 2026.1
Cadence has released Actran 2026.1 , and this version adds more capabilities to two key areas: high-frequency radiosity modeling and turbomachinery duct acoustics. It also makes it noticeably easier to...
View ArticleHigh-Speed Heterogeneous Integration with Multiphysics Analysis for TSMC SoW-X
2.5D advanced packaging is becoming increasingly critical as the demand for AI and high-performance computing (HPC) applications continues to rise and monolithic die size hits reticle limit. To sustain...
View ArticleFrom Pacemakers to ADAS: Verifying Systems Before Tapeout
Imagine discovering a critical bug in a heart pacemaker, not after deployment, not during final qualification testing, but months before the chip itself exists. At first glance, that sounds impossible....
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