In the overall world of EDA, the Design Automation Conference ( DAC ) is the biggest annual event for the industry. Nothing against DAC, but if you’re involved in functional verification as I am, the Design and Verification Conference and Exhibition ( DVCon ) in San Jose is more focused and arguably more important. Most people think of this as primarily a verification venue, but if you note the “and” in the name you’ll not be surprised that it often includes talks on chip and system design and architecture as well. This year is the 29 th for DVCon, which is a long run in the fast-changing environment of Silicon Valley. I’ve attended many of these events, perhaps most of them, and have been impressed by how quickly the program adapts each time to include hot topics and emerging industry challenges. This year is no exception. Since the entire program is now available online I’d like to leaf through it with you and highlight some sessions that look particularly promising. As always, I welcome your comments and any suggestions for talks that catch your eye. As usual, the technical program has two days of tutorials on Monday, February 27 and Thursday, March 2 with two days of technical papers and presentations in between. I couldn’t possibly be happier that the very first session of the four-day event is the “Creating Portable Stimulus Models with the Upcoming Accellera Standard” tutorial . Some of the most active members of the Accellera Portable Stimulus Working group (PSWG) will report on the status of the upcoming standard and show examples of how it can be used to address real-world verification problems. Cadence will be represented by Sharon Rosenberg. Monday is “Accellera Day” at DVCon, since the portable stimulus tutorial will be followed by a sponsored lunch with more updates on standardization work, followed by tutorials on the continuing evolution of the Universal Verification Methodology (UVM) and SystemC. The day closes with the opening of the “Expo” exhibition floor, where you can learn about the latest products and solutions from EDA, IP, and services vendors. The floor is open 5-7pm on Monday and 2:30-6pm on Tuesday and Wednesday. Of course, Cadence will have a booth there and we hope that you still stop by to say hello and see what’s new. Tuesday features more than 20 presentations, most of them deeply technical. Cadence’s Anirudh Devgan offers the keynote address on “Tomorrow’s Verification Today” and Uwe Simm presents “Flexible Indirect Registers with UVM.” We are also sponsoring a luncheon that features a panel asking “Application Specific Verification from Edge Nodes through Hubs, Networks and Servers – Are the Requirements all the Same?” Of course, there are some promising talks from other companies as well, addressing such topics as SystemVerilog, the UVM, coverage, constraints, optimization, and low-power design. Two presentation titles on Tuesday strike me as particularly clever: “Doing Funny Stuff with the UVM Register Layer: Experiences Using Front Door Sequences, Predictors, and Callbacks” from Doulos and “Error Injection: When Good Input Goes Bad” by Aletheia Design Services and Willamette HDL. In addition to the talks, Tuesday’s program includes a poster session with an amazing 19 contributions. Cadence appears here as well, with “Mixed-Signal Verification Methodology to Verify Type-C USB” and a reminder that DVCon’s scope goes beyond digital design and verification. Wednesday also has more than 20 technical presentations. Samsung presents “Emulation Based Full Chip Level Low Power Validation at Pre-Silicon Stage” featuring their results from using Cadence verification products. The two catchiest titles are “Yet Another Memory Manager (YAMM)” from AMIQ, a nice allusion to the Unix “yacc” utility, and the panel “SystemVerilog Jinxed Half My Career: Where Do We Go From Here?” There’s also a panel featuring portable stimulus users, and presentations on formal technologies, sequential equivalence checking, portable stimulus, analog/mixed-signal (AMS) modeling and verification, and more. Thursday offers sponsored tutorials by the major EDA vendors. I’ve been busy organizing speakers and preparing material for “Reinventing SoC Verification – It Is about Time” in which we cover several recent advances in verification, including advanced formal techniques, software-driven portable stimulus, metric-driven verification, and optimal use of multiple verification platforms. Cadence has a second tutorial “Optimizing IP Verification – Which Engine?” on Thursday afternoon, wrapping up a very busy four days. I believe that DVCon is a must-attend event for verification engineers, with much of interest for designers as well. I’m looking forward to both the conference and exhibition. Do you know the way to San Jose? Since the DoubleTree Hotel is only a half-mile from the airport, DVCon couldn’t be easier to find. I hope that you will be able to join us there! Tom A. The truth is out there...sometimes it's in a blog.![]()
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