Many system designers have been working with DDR4 RAM components in the past couple years and using them in system designs. With product demands of increasing performance and decreasing power budget, expectations for faster memory devices never stop. In 2013, even before DDR4 was widely used in mainstream designs, the DDR5 standard was announced to be in specification stage. Although the final version of the DDR5 standard is not yet available to the industry, the key features in DDR5 is publicly known: DDR5 will provide twice as wide bandwidth as DDR4 RAM and with more efficient power management. As the market is waiting for the availability of DDR5 devices, probably later in 2018, system designers are becoming anxious for the DDR5 spec. They want to know how much to upgrade their current system needs in order to support the new RAM performance and to take advantage of the increased data rates and power consumption level. As a result, they want to start prototyping designs with known DDR5 features as soon as possible, and then explore the use of DDR5 bus systems in their particular products. For experienced designers today, building a prototype using a new memory interface means to first gather the possible device models that represent the interface behavior, then validate it with a simulation tool or environment that takes in the new model and simulate the new features from, say, the DDR5 spec. Unfortunately for almost all designers, progress gets stalled here because there are no device models for DDR5 RAM. One might say that a memory device in write cycle is simply a receiver which can be represented using any existing IBIS receiver model. This could have been done 15 years ago. However, things are no longer that simple today. For those who have been designing systems using DDR4 RAM at higher speed, such as 3200Mbps, the reason is obvious. High data rate memory employs serial link filter techniques, such as equalization, to ensure signal quality. These filtering methods are modeled only by IBIS-AMI models and provided by memory and controller manufacturers. Since DDR5 would have faster speed and even lower voltage swing, equalization is more important. Therefore, system designers should have advanced models for both the controller and memory to simulate the new DDR5 interface. At this point, designers cannot obtain any of the models from the manufacturers. Now, we can all feel the designers’ pain: on one hand they want to eagerly build a system that is expected to work with the main features from DDR5 RAM; on the other hand, they are lacking the proper models for such experiments; further to their dismay, the models may not be available for quite a while. What worries designers the most is if their competitors get the models first, then their competitors will have an earlier product release taking full advantage of the DDR5 benefits. The difficulty doesn’t stop here: even when the models are available later, the designers still have no idea if their current simulation tool can provide the simulation capabilities needed to support the new data transmission features coming with DDR5. As a tool provider, one major goal should be to help remove the model dependency designers have and present options to designers so they can create their own models for an emerging new interface/technology. Can this be done? The answer is a big YES for Sigrity users. In fact, for those who have Sigrity SystemSI 2017, the solution is already in their hands! What a surprise, but this is true. Sigrity SystemSI has a built-in IBIS-AMI model generator: AMI Builder. This embedded tool uses the SystemSI GUI, takes in user defined AMI model parameters, creates an AMI model with user desired or default IBIS I/O buffer model. Our users, including our Cadence IP team, have been using this tool to create DDR4 models. Recently, some of them generated DDR5 AMI models with the required FFE/DFE technologies and successfully used them in testing system designs and predicting DDR5 behaviors. This actually puts to rest another concern many designers may have: even with a DDR5 AMI model, will my simulation tool support the DDR5 required features for a DDR5 bus? SystemSI is equipped with power-aware solutions using Cadence’s patented technology of using channel simulation in bus characterization and simulation. So, for anxious designers and SI engineers, there is no need to wait for the final spec of DDR5 or for the controller and memory manufactures to provide DDR5 models; Sigrity SystemSI can help you create the prototype today and understand how DDR5 should work in your applications. Therefore, no more worries! If you are currently using SystemSI and would like to learn more about AMI Builder, or you wish to have SystemSI and AMI Builder explore DDR5 designs, please contact the Sigrity team. For those attending DesignCon 2018 , we hope you will take the time to attend the paper presentations that discuss the successful users of Sigrity technology have had in modeling next generation DDR devices: DDR-4400 IP Model Development Using AMI Builder DDR5 Modeling Using Automated IBIS-AMI Modeling Technology Team Sigrity![]()
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