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How Can You Learn About Mixed-Signal Verification and Implementation Flows at...
The vast majority of SoCs today are advanced mixed-signal designs. The old mixed-signal world looked like an analog environment on the left bolted to a digital environment on the right. Depending on...
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Cloud Computing Design Challenges: An Engineering Journey
Earlier this year, we explored cloud computing and application-specific systems design, as Cadence Fellow Chris Rowen urged us to "follow the data" to understand evolving electronics-design...
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Add a View of Your Package Substrate in Your IC Layout Tool for Maximum...
We have all heard about co-design, how it is going to get us to market on time, reduce our layer counts, and give us the ability to trade off design decisions at different layers of the system...
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Cadence DAC 2014 and Denali Party Update
The 51st Design Automation Conference (DAC) will take place June 1-5 in San Francisco, and Cadence is preparing a number of activities. This year Cadence is participating in technology sessions,...
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EDPS 2014: Rethinking the Electronic System Level (ESL) Design Flow
Last year, analyst Gary Smith proclaimed that a "working" electronic system level (ESL) flow had finally arrived. At the recent Electronic Design Process Symposium (EDPS 2014), a panel of ESL experts...
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e and SystemVerilog: The Ultimate Race
For years we've watched the e and SystemVerilog race via countless presentations, articles, and blogs. Each language is applied to SoC verification yet the differences are well documented so any...
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Whiteboard Wednesdays - Verifying Your Designs with Simulation VIP
In this week's Whiteboard Wednesdays, Tom Hackett takes a closer look at simulation verification IP (VIP), and how these IP cores help verify designs with protocol checks, test sequences, and other...
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Don’t Miss Embedded Vision Summit West on May 29
Embedded Vision Summit West 2014 on May 29 at the Santa Clara Convention Center provides a unique opportunity for engineers to learn about the hottest technology in the electronics industry: embedded...
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See Cadence RF Technologies at IEEE International Microwave Symposium 2014
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IoT's Promise Shadowed by Privacy Questions
The Internet of Things (IoT) will help society do more with less, drive efficiencies, and light a fire under economic growth, but concerns around change-averse industries and user privacy may delay...
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Whitepaper: Hierarchical Timing Analysis Tradeoffs, and a New Methodology
Given the complexity and time-to-market pressures behind today's semiconductors, nobody has time for redundant analysis and verification. For this reason, most static timing analyzers today support...
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sync and wait Actions vs. Temporal Struct and Unit Members
Using sync on a temporal expression (TE), does not guarantee that the execution will continue whenever the TE seems to succeed. In this example, the sync action will miss every second change of...
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High Yield Analysis and Optimization - How to Design the Circuit to Six Sigma
Why high yield analysis?One failed memory cell out of millions cells will cause the whole memory circuit to fail without ECC (error checking and correction) techniques. That is why memory designers...
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What's Good About Allegro PCB Editor Show Measure for Dual Units? 16.6 Has It!
The Allegro PCB Editor 16.6 ‘Show Measure’ command now displays results in database and alternate units. Alternate unit display requires the enablement of the user preference variable...
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Webinar: Addressing MCU Mixed-Signal Design Challenges
We know IC and system design is changing before our eyes. Not too many years ago, 80 percent of a design started from the ground up while 20 percent was leveraged or re-used from previous projects....
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Whiteboard Wednesdays - Promises and Challenges of DDR4 Memory Technology
In this week's Whiteboard Wednesdays, Kishore Kasamsetty provides a history on DDR4 technology. He also walks you through the improvements of DDR4 over DDR3, as well as the memory standard's...
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Virtuosity: 19 Things I Learned in April 2014 by Browsing Cadence Online Support
Plenty to keep you busy this month. Lots of RAKs, videos, and new Quick Start Guides and FAQs.Application Notes1. Using Annotation Browser with Virtuoso IPVSLearn how to invoke the Annotation Browser...
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DAC 2014: Semiconductor IP Trends Revealed at “IP Talks!”
Want to know more about the design and verification IP that makes advanced system-on-chip (SoC) design possible? There's no better place than IP Talks!, a series of ongoing presentations at the...
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Embedded Vision Summit: Focus on Autonomy and Recognition
We often think of better electronic systems design in the context of the improved power, performance, and area of its various components, from generation to generation.But some eras introduce new...
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Google Project Ara: What Engineers Need to Know
Google's Project Ara, the so-called"Lego" smartphone architecture unveiled in April, means intriguing new design options and opportunity for IP providers in the near term and raises profound questions...
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