Stacked memory is becoming increasingly common in IC package substrates; with that memory being sourced from multiple vendors, managing all the different combinations of your logic die(s), memory components, controllers, and BGAs in a way that your package functions properly in all configurations while still minimizing the per-unit cost gets harder with each new generation of substrates. Pick up a copy of the 16.6 June 2015 release of Cadence SiP Layout XL tool to simplify your life. Newly added to the tool is a command that helps you to define a single database that combines all the possible variants of the die stacks. This allows you to optimize the common elements of the design with ease. When it comes time to manufacture and verify a specific configuration, the tool can create a new database which includes only the elements of that variant. You can run additional assembly and manufacturing checks on that database, run SI checks, send it to your foundry for validation, generate documentation packages, and more. To learn about this new tool and how you can help define its use model and focus, read on! The Define Variants Interface The Define Variants command is a fresh new command first available as a beta feature in the QIR7 quarterly release of 16.6. With the June 2015 update, it is a production command available in your Manufacturing menu as “Define Variants…” Whether you have three sources of memory chips, seven different options for total available memory, or two packages that same stack can be assembled in, the tool will (eventually) support them all. For now, a heavy focus has been placed on the most widespread application of variants – stacked memory. Taking a closer look at the variant definition tool itself, we see a form elegant in its simplicity: Identify all the components that belong in this variant of the substrate, select layers that are (or are not) part of the configuration, and you’re done. When you generate a new database for a specific variant definition, elements that aren’t part of this substrate will be stripped out automatically for you. Verify things with ease by having the resulting database automatically opened in a second SiP Layout window for you, ready for running Assembly DRC or custom RAVEL-based design rule checks. The extracted database is fully ready for signal/power/thermal analysis, too. You can even batch generate databases for all the variants defined with a single button push, too. Just be careful if you have a lot of variants in the database and are extracting all of them at once – that could be a lot of new windows opening up! Don’t worry about renaming the reference designator of a component or changing the name of a layer, either. The tool will watch for these and automatically compensate for the changes by updating the information for each variant. Have an Idea for Making This Flow Even Easier? This is a brand new, exciting tool for you to use. But, we need your help! What elements can be varied in your designs? How do you optimize across all the different combinations and configurations? What information do you need to see (or not see) while working in the combined master database? Perhaps you need to remove sensitive IP from the resulting database so it can be more easily sent to a foundry for fabrication. Be sure to let your Cadence customer support representative know! With future releases of SiP Layout, your needs could be reflected in the increasingly fully featured flow for IC package variant design! Bill Acito Jr.![]()
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