The PCI-SIG Developers Conference happening today and tomorrow will be yet another exciting PCI-SIG event that Cadence is proud to participate in. We’ve been attending and showcasing technology at these conferences for many years now, sharing news and insights about our verification IP, controllers, and PHY solutions. Cadence was the first commercial PCI Express 3.0 IP provider, and has continued that tradition by engaging with key server customers for PCI Express 4.0. The latest incarnation of the specification doubles the maximum bandwidth for a 16-lane configuration to a whopping 256 GTps. This protocol revision is driven by the need for more data to be transported faster across the interface. Technology adoption in the consumer space is a key factor: the amount of data transferred across the Internet by the end of 2016 is estimated to be a zettabyte (1 followed by 21 zeroes!), according to a Cisco report . Video comprises a significant portion of this traffic. The same Cisco report states that every second, nearly a million minutes of video content will cross the network by 2019. PCIe 4.0’s doubled speed relative to 3.0 has benefits for all elements of the infrastructure space: server, storage, and networking applications. Customers are demanding these advanced protocols in advanced process geometries and Cadence is at the forefront of delivering the latest technology in this space. The Cadence PCIe 4.0 Controller IP is designed to the latest specification revision and is available to customers. We also have a PCIe 4.0 PHY in silicon. Verification IP for PCIe 4.0 is also available. At the same time, the available performance improvements with new process nodes set a higher bar for power and area for the existing versions of the protocol. Cadence has PHY solutions for both Gen3 and Gen2 in 16nm that are extremely low power and highly attractive even in the mobile space. We are engaged with phone and tablet manufacturers in bringing a previously “desktop/laptop-oriented” protocol to leading-edge mobile platforms. Integrating these advanced solutions in new nodes with a standard that is under development can be challenging. Cadence provides integrated solutions that build on the soft IP, hard IP, firmware, and verification IP to build a sub-system that accelerates customers’ development with 3 rd party IP. Cadence will be at PCI-SIG Developers Conference in Santa Clara again this year with a set of demos and presentations highlighting our solutions for these new trends. Our IP architect, Gopi Krishnamurthy, will speak at the event on “ Emulating a PCIe 4.0 Controller on a Real System ”. We invite you to attend the event and connect with our key architects and our technical experts for more information on how we can work with you on accelerating these advanced designs. Arif Khan![]()
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