The MIPI CSI-2 (Camera Serial Interface) specification is celebrating its tenth birthday these days and the party is quite big with millions of mobile devices out there, passing every pixel from the camera sensor to the application processor through this interface. The success of this protocol is due to a very robust architecture that enables high-speed traffic with low power consumption and cost-effective implementation. The CSI-2 protocol has been enhanced several times during the last decade and these days the MIPI Camera working group is working on a new enhanced version, CSI-2 2.0 , to address the ever-growing requirements. First, let’s review the ‘Why?’—What are the driving factors that lead CSI-2 protocol enhancements? Growing bandwidth requirements: Higher cameras resolution leads to higher bandwidth needs. Today’s PHY (D-PHY) bandwidth is 1.5Gbits/s per lane, with typical x4/x8 lanes implementation (6 or 12Gbits/s ), will not be enough soon. Internet of Things (IoT) needs: In the new era when every device is connected to the cloud and has a camera sensor, low resolution with very low power limits will generate a new set of challenges. Automotive: The new "intelligent" car is going to be aware of everything around it. It’s going to take multiple cameras that send simultaneous, real-time information to the processor. Again, a new set of challenges. Machine vision: The industrial world is progressing fast and more and more cameras are now part of it, creating yet another different segment and usage model. So how those requirements are going to be addressed ing the new CSI-2 2.0 specification? The following are few of the enhancements that are being discussed at the working group: Data scrambling helps to improve signal integrity in order to enable higher speed/frequency Increased bus width between the controller and the PHY (PPI interface) is essential for addressing growing bandwidth needs (more data per cycle) Higher number (4=>16) of virtual channels are needed when multiple cameras operate simultaneously and use interleaved data Support for I3C as the control interface (instead of I2C) enables the transmission of pixels through the control interface (with very low rate though) and saves power, also can be used for downloading the camera firmware more effectively The CSI-2 2.0 specification is planned to be released early next year. Cadence already provides support for the new CSI-2.0 features (as well as I3C) as part of its MIPI verification IP portfolio . If you like to meet Cadence MIPI experts F2F, don’t miss the MIPI demo day in Taipei next week, Thursday, October 29, 2015. Moshik![]()
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