Earlier this week was the Cadence Mixed-Signal Technology Summit. Since I was the emcee, I spent the entire day there and saw all the presentations. I am not going to try and detail everything that was said in every presentation: you had to be there! But as I usually find in these sort of all-day summits, there turn out to be a couple of themes that ran through the day. Christine has already blogged about the keynote by Professor Bora Nikolic of UC Berkeley. Berkeley is faced with flat enrollment in electrical engineering and exploding enrollment in computer science. In fact the daughter of a friend of mine (a CS major!) told me that it is crazy and now over 10% of the entire intake to the university is majoring in CS. Anyway, Bora realized that if any chips were going to be designed that they needed to leverage what the CS students already knew: the languages such as Python and Scala, methodologies such as agile development, and so on. Even in analog they have created the Python-based Berkeley Analog Generator (BAG), which can do iterative simulation to home in on a working block as shown below. One thing that Bora pointed out was an effect of Moore's Law in the mixed-signal world. The digital logic gets smaller, faster, and lower power. Everything else, even static memory, does not. Analog has it even worse with the transition to FinFET since it also has to absorb the hit of quantization: you can no longer vary the width nor length of a transistor, you can just have a different number of them. The effect of this is to transition analog design from what it used to be, largely trying to design high-precision analog circuits, to what it is today, good-enough analog designs with digital logic to tune, correct, and filter. When tens of thousands of gates are basically free, this changes the tradeoff completely. It is a little like the way to get good audio: either design very good (and expensive) speakers, or use okay speakers, put a microphone in the listening position, and then use DSP techniques to correct the signals to take account of imperfections in the speakers and the room acoustics. For example, here is an article in Computer Audiophile (who knew that was a thing?). So all analog design has become truly mixed signal, with an analog portion and a large and an ever-growing digital portion. Designing an "analog" block such as an ADC still splits up into two parts, design and verification. But it is no longer just a layout editor and a SPICE simulator as it seems to have been for decades. Subodh Reddy of Maxim gave a presentation on Model-Based Verification of Mixed-Signal SoCs , and Régis Santonja of Freescale in Toulouse (France) gave a presentation on AnaVip: a UVM-MS Component to Drive and Monitor Analog Signals . Although the focus of Subodh's talk was verification and of Régis's was test, the methodologies were very similar. SystemVerilog Real Number modeling (SV-RNM) is becoming increasingly important although there is still a lot of WREAL use. There are also lots of subtle issues about when to sample the analog to get enough precision without the run time increasing prohibitively. The solution is to create models of the analog that can be run against the digital simulation. But this runs into the human factors issue that the analog designers are not that interested in, nor possess the skills to create models. The digital designers need the models but don't understand the analog well enough. So the only real solution is to have a team of verification engineers who are responsible. It is not a trivial task, not least since the analog designs are in development and so not stable, meaning the models need to be adjusted to keep up...in fact, not unlike the problem with modeling for virtual platforms that I blogged about earlier in the week. As for doing the design, Cory Mathis of MathWorks (they named the company after him!) gave a presentation on Connecting MATLAB and Simulink to Virtuoso AMS Designer for Functional Verification of Mixed-Signal Systems, and Chris Rowen, the CTO of Cadence's IP group, gave a presentation on Digitally Controlled Analog with Tensilica Embedded Processors . Despite the different titles, both presentations covered both design and verification. In a modern process with all the parasitics, there is no such thing as design without verification. Verification is less about checking that the design is "correct" but rather is an iteration between the two. MathWorks' two main products, MATLAB and Simulink, can be used to create everything from mathematical models of designs, to linking up basic analog elements and more. There is a capability to write out SystemVerilog and thus get between the MATLAB world and the AMS Designer world. Chris, who had the unenviable slot between the rest of the day and the social evening, talked about using DSPs based on Tensilica IP to create much of the digital logic needed to accompany the true analog portion. The example he used was a multi-stage ADC where the processor calculated the parameters required to correct the stages. The example showed an additional couple of bits of precision. It may seem like a lot of overhead to use a processor to do that, but they can be very small. Plus, since the processor is only needed occasionally to monitor what is going on and recalculate the corrections, the same processor can be used for many ADCs. So in conclusion, analog design is increasingly digital design, and the two major challenges are alternative mechanisms for generating the analog portion, and verification methodologies that smoothly handle the mixed design and the spectrum of skillsets the engineers have from deep analog expertise, to computer science with almost no knowledge of even what a transistor is. That's quite a broad spectrum.![]()
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