Designing connected devices comes with the added challenges of small form factor and long battery life requirements. SoCs integrating the processor, radio, and sensors provide an answer, as does MEMS technology, which miniaturizes sensing and energy harvesting. But since both are fabricated on separate processes and die, this presents a multi-die SiP integration challenge. Ian Dennison, sr. group director of R&D at Cadence, and Tim Menasveta, CPU product manager of Cortex®-M0 and Cortex-M0+ processors at ARM, together addressed this SiP integration challenge during a training session on Wednesday, Nov. 11, at ARM TechCon. First, some background on MEMS for IoT applications. MEMS are miniaturized mechanical sensors and actuators fabricated with semiconductor technology. They deliver precision measurement of acceleration, speed, position, pressure, and many other factors. MEMS are ideal for IoT applications because they are not only rugged, low power, and low cost, but they also deliver high reliability, accuracy, and sensitivity, noted Dennison. Meeting Form Factor, Power, and Cost Targets For differentiation, many IoT products are miniaturized to meet form factor, power, and cost targets for applications like wearables. This approach is driving IoT designs to SiPs and SoCs. An SoC and MEMS component can be integrated in many ways – the MEMS die can be stacked on top of the SoC and connected with bond wires, or connectivity can be accomplished using TSVs. A design flow that can support an SiP product integrating MEMS sensors and an SoC taps into tools from ARM, Cadence and Coventor, a Cadence Connections partner. From ARM, there’s IP and development tools. Cadence’s offerings include the digital design and signoff platform, along with simulation, mixed-signal and low-power, SiP layout, and PCB design tools. Coventor provides a “Lego-like environment for building a MEMS device,” said Dennison. Design Flow for an SiP product integrating an SoC and MEMS sensors As an example of a MEMS sensor, Dennison discussed a single-axis accelerometer based on a comb capacitor design with a force-feedback control loop and a sigma-delta control circuit. Coventor’s tool can be used to create the multi-physics sensor model, which would then need to be simulated with the electronics and control circuit (consisting of analog and digital components in a Virtuoso schematic). Cadence’s Spectre Accelerated Parallel Simulator can do this, providing the engineering team a view into any improvements that they can make to the design. During his part of the talk, Menasveta noted that most connected sensor nodes have an ARM® Cortex-M processor at their core. The Cortex-M0 platform, with their efficient 32-bit architecture and programmability in C, is ideal for custom IoT SoCs, he said. Menasveta also discussed the ARM IoT Subsystem for Cortex-M , an IP block with low-power features that helps designers create IoT endpoints faster and with lower risk. “ARM believes assembling of IP blocks is not a differentiating value for our silicon partners,” said Menasveta. “We want our silicon partners to focus on adding their differentiating value by integrating their high-performance radio or MEMS sensor or other controllers.” Continuing the discussion on differentiation, Dennison, noting that 85% of all custom SoC design starts are mixed-signal designs, noted that each block in the design provides opportunities for differentiation. Off-the-shelf IP also can help designers quickly differentiate their IoT SoC, he said. “ARM, Cadence, and Coventor have teamed to provide all the necessary integrations and fabrics to achieve IoT solutions,” Dennison concluded. Christine Young Related Articles ARM's Mike Muller Announces a New Core, a New Instruction Set, and Security Layer![]()
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