UC Berkeley Professor Borivoje Nikolic sees agile software methodologies as an answer to infusing the chip design process with greater efficiency. “Twenty years ago, technology people had fun making fun of ITRS predictions,” said Nikolic during a keynote talk at Cadence’s Mixed-Signal Technology Summit in October in San Jose. “Nowadays, they have a hard time making the cell as small as predicted. As a result, we have lost one technology generation of scaling over the past couple of years.” UC Berkeley Professor Bora Nikolic addresses an audience at Cadence's Mixed-Signal Summit in October. Scaling is slowing down for a few reasons. For one thing, it’s hard to scale SRAM, which occupies half of a typical die, Nikolic noted. While some might see the end of scaling as a problem, Nikolic sees an opportunity to streamline the development process for complex SoCs—and to make these chips more energy efficient to continue generating performance gains. Performance Limitations Emerge Transistor scaling led to performance increases over time until the early 2000s. That's when engineers hit power limits and frequency also flattened. They could no longer generate more performance in traditional ways. So, engineers began adding more cores in parallel, but today, says Nikolic, we are seeing saturation. Parallelism, he said, was a one-time gain. What can be done to address the performance limitations? There are energy efficiency gains from using simpler cores or running more cores at lower Vdd/frequency. “But we can’t have simpler general-purpose microarchitectures, and there are limits to supply scaling and how low we can go with a supply and how efficient a core can be, “ said Nikolic. ASICs were considered an answer, but with NREs up to $100M, long development cycles requiring multiple revisions, and low reuse, the number of ASICs starts have fallen, noted Nikolic. Enhancing Energy Efficiency of Designs At the UC Berkeley engineering department, researchers have tried to find commonalities among many application domains. Explained Nikolic, “There’s a certain set of motifs, relatively limited, that need to be implemented efficiently for these application domains to be efficient.” The department has identified 13 motifs, including finite state machines, circuits, graphical models, and matrix manipulations. Specialized processors would implement these domains, and mapping software would map them to a particular engine. Nikolic noted that this is an area under development. Bringing Agile Design Techniques to Hardware Development At Berkeley, Nikolic and his colleagues are promoting the idea of agile design , taking elements of an approach typically used in software development and applying them to the hardware world. Nikolic believes that by borrowing these characteristics from software development, chip design can be agile: Design a series of prototypes with small teams Use higher level descriptions with modern languages Design generators, not instances, which allows agile validation and enables reuse Treat open source as a friend, particularly when it comes to “standard” chip components Use rapid design flows Consider a typical SoC as an example. Nikolic explained of the agile process, “Let’s abstract the chip into a small set of blocks that are as simple as can be to validate the interfaces first and then build the smallest chip that we can. We can use software validation, but we can also spin that kind of chip and fabricate it if we like. “Every block would be built with a generator. The idea here is to validate all the interfaces of a tiny chip, validate the generators, then scale up the design using the generators.” During his keynote talk, Nikolic also shared some examples of tools developed by the Berkeley engineering department to facilitate agile chip design. One is Chisel, an open-source hardware construction language based on the Scala embedded language that features functional and object-oriented programming and enables construction of generators rather than instances. Another is Berkeley Analog Generator (BAG) , which codifies design intent to simplify the creation of analog/mixed-signal (AMS) circuit generators. “Efficiency is achieved through specialization and this specialization is the value that customers perceive,” said Nikolic. “That’s why they buy the chips.” Christine Young![]()
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