Without a doubt, there’s plenty of innovation happening in the electronics industry right now. The burning question is, how can engineers continue to accelerate this level of innovation while also achieving power, performance, and area (PPA) targets? That was the key topic addressed by Subramani Kengeri, VP of CMOS Platforms at GLOBALFOUNDRIES, on Thursday, Dec. 10, at Cadence’s Digital Implementation Summit. “We spend billions of dollars in R&D to get the very best technology from a PPA point of view, but if that is not translated into real product, then we have lost a big chunk of value,” Kengeri told attendees at Cadence San Jose headquarters. Indeed, scaling is continuing from a technical standpoint – we have visibility today into 5nm. But are we scaling at any cost, and are we doing so at the expense of energy efficiency? Subramani Kengeri from GLOBALFOUNDRIES addresses an audience at Cadence's Digital Implementation Summit on Dec. 10. 28nm a Sweet Spot for Now As usual, wafer costs continue to increase, particularly after 28nm, said Kengeri. In fact, he noted, increased costs from more complex processes are offsetting the benefits of die shrink, slowing down future scaling. “The ROI on any new product has to be revisited. 28nm will remain a sweet spot for a while,” he noted. How to reap benefits after 28nm? As engineering teams contemplate their next node, there are debates around FinFET and FD-SOI. Each solves a different market need. GLOBALFOUNDRIES has spent over 10 years researching both in parallel, ultimately siding with the industry and prioritizing the FinFET process. While it has consistently delivered better energy consumption, the performance of first-generation FD-SOI has simply lagged behind that of FinFETs. However, what about applications that are energy-conscious and don’t require the performance level of FinFETs? For this area, GLOBALFOUNDRIES has an answer in its 22FDX platform reference flow, the industry’s first 22nm FD-SOI technology. The 22FDX flow provides FinFET-like performance at ultra-low power consumption (0.4V operation) at costs similar to 28nm planar technologies. Some noteworthy data points on the flow: It provides 70% lower power compared to 28HKMG It results in a 20% smaller die than 28nm bulk planar It offers a lower die cost vs. FinFETs Flexibly Trade Off Between Performance and Power “This is going to enable innovation in interesting ways that haven’t been possible in the past,” Kengeri said of 22FDX. “Put this in the hands of creative designers, who will have additional knobs they can play with, and you can have wonders. That’s what we’re talking about [regarding] accelerating innovations.” The “knobs” that Kengeri referred to include these capabilities: Software-controlled transistor body biasing, which provides a flexible tradeoff between performance and power. You can basically apply different back biases to different modules and control them through software at the level of granularity needed. Integrated RF, so you can include RF function in your design cost effectively and with energy efficiency, rather than having to use a separate RF chip Post-silicon tuning, which allows you to selectively increase performance or lower power In November, Cadence announced that its digital and signoff tools are enabled for the 22FDX platform reference flow . Cadence also worked with GLOBALFOUNDRIES to develop a Process Design Kit (PDK) for the platform. “22FDX accelerates innovation across a very wide range of applications,” said Kengeri. “Typically, FinFET or previous [processes] are optimized for specific market segments. This technology allows you to extend the value across a very wide range of applications.” “22FDX is the right technology at the right time,” he told the summit audience. “Let’s lead the next wave of innovations together.” Check this page soon for online proceedings from our Digital Implementation Summit. You can already view presentations from our Front-End Design Summit, held on Dec. 2, from the same page. Christine Young![]()
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