In any advanced node, one of the most important pieces of IP is a high-performance SerDes PHY. Of course, what counts as high-performance depends on the node. At the current 16nm node, 16Gbps is the sweet spot. The reason that SerDes is so important is that almost all interface IP such as PCIe, USB, SATA, and more rely on a SerDes PHY to handle the interfaces between the SoC and the outside world. A clean PHY is one where the signals are well enough shaped that decoding them at the receiver works flawlessly. I'm sure you've seen plenty of eye diagrams showing off how clean the signal is with a large eye so that the difference between a 1 and a 0 is clearly detectable. The PHY can be common to all the different protocols, with different logic behind depending on the details of the protocol, or, in the case of a multi-link PHY, more than one, so that the exact protocol used can be configured after manufacture. This configuration is what makes it such an important piece of IP. Not only does the top performance define how fast data can be got on and off chip (per pin), but the same IP can be used as the basis for the full portfolio of important interface IP, all of which is either serial or multi-lane serial (for example, 4 lanes of 16 Gbps, which give 64Gbps of bandwidth). Cadence offers a 16Gbps multi-protocol PHY IP that is a hard PHY macro consisting of a PMA layer and a soft PCS. It provides continuous frequency range support from 1.25Gbps to 16Gbps, with the capability to equalize channel loss up to 30dB at Nyquist, and complies with the PCIe 4.0, 10G-KR, RXAUI, XAUI, GbE/SGMII, SATA3, and HMC-SR specifications. The IP supports low-power mode (such as L1 sub-states for PCIe) for power-efficient applications. Implemented on TSMC’s 16nm FinFET process, the PHY IP can help control costs and power for high-performance designs. The table below shows many of the protocols that can make use of this multi-protocol PHY: Typically, a PHY consist of two modules: the physical media attachment (PMA) and the physical coding sublayer (PCS). The PMA is the analog part of the SerDes implementation, while the PCS is a digital block establishing the functional link to the protocol supported. A multi-protocol PHY implements support for multiple protocols by optimizing the usage of signal-path blocks needed for each protocol. In the case of the PMA, this support consists of a common high-speed SerDes signal path across multiple protocols. For the digital PCS, it entails a configurable design that uses the same signal-path components multiplexed as needed for different protocols. This approach leads to optimized die area and, as a result, lower SoC cost and an accelerated design schedule. By tapping into a single, multi-protocol PHY IP, an SoC designer can reuse many of the common design building blocks, enjoy a much simpler design verification process, benefit from a faster bring-up and characterization process, and perform only a single test-chip tapeout. Other advantages of a single PHY IP: Create a single design that supports multiple applications—the advanced transceiver and clocking architecture minimizes power and the number of logic components required Change protocol during the design process via a soft code change, not a full chip redesign and without the headache of readjusting the chip floorplan Relieve engineering burden and reduce overall design costs by getting multiple uses from a single IP In addition to using the same PHY for multiple protocols (multi-protocol), the Cadence PHY supports multi-link with a single PHY able to support multiple protocols on the same chip. This support makes it possible to build SoCs where the actual protocol used can be configured. So, for example, a single SoC could configure as a 16-lane PCIe (for networking), or as 8-lane PCIe with 8 lane SATA (for storage) or as 12-lane PCIe and 4-lane 10G-KR (for compute), and so on. This flexibility reduces risk and amortizes the cost and NRE of developing and bringing an SoC into manufacture over a wider range of end-markets. Modern SoC designs incorporate more and more interface protocols in a single chip to meet demands for product flexibility, fast time to market, and cost competitiveness. For example, in the above block diagram of a (imaginary) network processor, all the blocks in blue take advantage of the multiprotocol PHY. This PHY IP provides the market an easy-to-use unified PMA + configurable PCS approach in conjunction with cost benefits. The IP offers an optimum PHY solution to satisfy application needs ranging from data rates of 1.25Gbps to 16Gbps and covering most major and popular standards, such as PCIe, SATA, USB 3.x, SGMII/XAUI, 10G-KR, and others.![]()
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