PCIe Gen4 is bringing new possibilities to servers and virtualization. The interface increases the bandwidth and value of data transmission from server to server, switch to switch, and server to storage, enabling even larger dataset analysis and other complex cloud services. High-speed SerDes technology is used to implement these high-speed connections, often at advanced nodes such as 14/16nm. To be sure, it's becoming increasingly difficult to create robust designs while meeting short project timescales.Why not partner with a leading IP provider instead of doing your own IP design? Cadence, for instance, provides high-speed SerDes IP: a 16Gbps PHY that supports multiple protocols (see Figure 1 below). Figure 1 – Cadence's 16Gbps multi-protocol PHY Unique Multi-Link Configurability Cadence is also the first to market with a multi-link SerDes, which supports different protocols running on links in the same bundle or macro of SerDes. This means each link can be configured to 1 of the 14 protocols supported by the PHY. To simultaneously support different protocols, there are two PLLs embedded per common block.The configuration is software enabled through the registers. While the SoC is running, the SerDes can be halted, reconfigured, reset, and restarted. The turnaround time for this process is “awesome." The PHY also offers long reach and high power efficiency for green datacenters. Demo at DesignCon Cadence will be demonstrating a PCIe Gen4 testchip operating at 16Gbps at the 2016 DesignCon Expo, held at the Santa Clara Convention Center this week. Get more details about Cadence's participation at DesignCon here . Steve Brown![]()
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