We are all familiar with it. Every year, designs get faster, smaller, and more complicated. Whether your newest package has a towering stack of memory dies placed into a cavity or a few massive flip-chips with critical bus lanes between them, it never fails. The database that represents that complex package is, itself, growing more complex. Co-design dies, flow planning bundles, via structures for fan out and shielding of critical nets, you name it. As a group, we continue to find ways to achieve more with less – more computing power from less power in less space. How, then, do you ensure that your SiP Layout or Allegro Package Designer database is optimized to allow you to work as efficiently, as quickly, and as intelligently as possible? Keep reading, and we will walk you through some of the tools designed to help you, how and when to apply them, and what to think about when you are ready to start your next layout – or if you need to update a large design already in production. Basic Design Best Practices Regardless of the database you are using, there are a few rules that apply that will always help you to get better performance from your tool. The same is true in the Cadence package design tools. What are the key tenets to make sure you consider whenever you start a new design, then? Identify your power and ground nets. As pin counts increase dramatically, power and ground numbers can skyrocket. When you don’t identify these nets as being for power or ground, though, the system will treat them like signal nets. That means trying to build a net schedule for routing the pins together, displaying those rat lines, and in some cases even attempting to compute delay values. So, when you establish your net list, make sure you take a few seconds to identify those voltage nets. They should have a voltage property, a power and ground net scheduling, and possibly even the no rat property. It’s a small thing, but it makes a big difference. Set up your constraints and regions wisely. The more complicated your constraints are, the longer DRC checks will take, as the system must ensure that it validates everything you’ve told it is necessary for your design to be successful. Do you need a constraint region under every die? Or just under your dense flip-chips? Is it necessary to have route keep out areas everywhere you’ve placed them? The fewer rules you impose, the faster your DRC checks will run. But, it is not just your DRC updates; remember, because online DRC checks are updated when you modify objects like routing, having fewer constraints will speed up nearly all flows you have. Leverage dynamic shapes. Dynamic shapes can save you hours of time throughout the course of a design. But, they can also slow you down if not managed properly. Do you need to add that ground plane on a layer before you do any routing on it? Or can you do your signal routing first, then add the shape and make routing tweaks if necessary? Here’s a hint: the second option will be faster than the first! Everything in the proper order. The Allegro database is wonderfully versatile and powerful. But, not properly managed, it can get cluttered with things that don’t need to be there. So, plan your design flow accordingly. Don’t degas your shapes before you do your routing (or, really, until you are ready to start dealing with metal density and balancing concerns before manufacturing). Do you need to fillet your routes when you are just doing feasibility routing? That might be unnecessary. If you are doing a chip-scale package, it is probably not necessary to do your plating bar routing until the end, as you can go from fingers right out to the edge of the package. By making sure that you build up your substrate in the best possible order, you can make each step as fast as possible. Don’t add things to the database that aren’t necessary. This could be something as simple as extra layers that aren’t necessary or padstacks in your via lists that aren’t in use. Or, it could be less obvious. Do you have unplaced components that are unnecessary because of an ECO or some other change, or maybe clines routing between pins/vias that are covered by a filled shape? You don’t need both! Remove these objects, and your database size will shrink. Consider turning off undo/redo. For large designs with a high number of dynamic shapes and highly constraints nets, consider turning off the undo/redo functionality. You can do this through Setup -> User Preferences. While this may sound unintuitive, turning off these features negates the need for the database to manage the ability to roll back changes to the design or to make them again and ensure the same results. By turning off the commands, you will also shrink the in-memory footprint of the tool, which can impact overall system performance if you have many other applications running. Those are just six very common, but powerful, concepts to keep firmly in mind as you do your design work. If you are always planning ahead, you will be astounded at just how much faster you can work. A little patience and forethought go a long way! Assessing Your Design for Performance Bottlenecks and Potential Problems It is all well and good to design things perfectly from the moment you type “new” on the command line to start a new layout. But, designs go through many iterations (and designers’ hands) in their lifetime. If you open a design and find that performance is much slower than what you think is reasonable, are there ways to determine what is causing the performance issues? You bet there are! Whether you are using SiP Layout or Allegro Package Designer, the first two tools you should turn to are both in the Tools menu. Run the Database Doctor’s Performance Advisor. This incredible tool will do a thorough check of your design and give you a detailed report of changes you may be able to make to improve your performance. While you’re here, go ahead and run a database check; it takes but a moment or two, and will ensure that there is nothing of concern that might be the cause of future troubles. After running the database doctor, take a look through the Package Design Integrity list of rules. There are many checks here which you can selectively run. Not only will they alert you to things like missing voltage properties on your power nets, but they can also find potential manufacturing and quality issues like vias misaligned with pins and clines with small bends that aren’t necessary. Running these two tools can help point you at many things that will slow you down. The time they take to run will almost certainly be less than the extra time you would spend working on your design without them. Don’t forget: You can add your own checks to the Integrity Check list. So, if you have something you know happens frequently in your design flow, consider implementing your own rule to check and correct it. There are helpful resources in the online help pages which can get you started with writing integrity checks of your own. Have a Suggestion? Do you have something you do that you’ve found makes your work faster? Share it with us, and we’ll follow up this post with another in the future. Let others benefit from your knowledge. They will thank you for it! Or, if you have a suggestion for an integrity check, or just something you find frequently causes your designs to bog down, your Cadence customer support representative is anxious to hear from you so we can improve the tool. Bill Acito Jr.![]()
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