Automotive chips often suffer from a limited chip interface in which most of the pins are analog. But increasingly, high-precision analog is being implemented not as pure analog layout, which suffers too much from process variation, but as a mixture of analog along with a lot of digital gates to tune and correct it. There is often an embedded microcontroller, which is obviously digital. These two trends mean that the number of digital gates on the chip is going up fast and those digital gates need to be tested. The challenge is how to do that. On a big SoC that goes into a smartphone or a computer, this is not a problem since there are lots of digital pins available. But in automotive, there are often few to none and adding extra pins makes the chip larger and increases costs. The standard four-pin approach uses JTAG’s four-signal interface to communicate with the TAP controller. Can we do it with fewer than four pins? If using scan test, then we can get down to three pins and a single scan chain. The three pins are the scan clock, scan in, and scan out. However, as the number of digital gates increases remorselessly, the test time goes up unacceptably using just a single scan chain. A second scan chain would reduce the test time but would require additional pins. Two changes can be applied to provide a better solution. The first change is to use scan compression. This adds a register, the Smart Scan deserializer, to the scan architecture that holds a relatively small number of bits. Using what is in effect a large XOR gate, this is expanded (by anything up to 100X) to create the actual scan chain data. An equivalent XOR gate at the other end of the chains compresses the scan out data into the Smart Scan serializer, which can then be scanned out. This results in a huge reduction in test time. Using 2D Elastic Compression as is incorporated into the latest Cadence test offering, Modus Test Solution (see my blog when it was recently announced) can support even greater compression, although that is probably academic for these automotive chips that contain relatively little digital logic compared to a huge digital SoC like the ones for cellphones or graphic accelerators. When pins are tightly limited, the second change is to merge the test clock and data in pins into a single digitally encoded pin, which will save some cost. This can be done by switching to Manchester encoding on the scan in pin. This is a better approach than the alternative way to get rid of a pin, which is to keep the clock but merge scan in and scan out onto one pin, alternating the direction. This alternative prevents overlapping scan, thus increasing test time. Manchester encoding was invented at the University of Manchester in England in 1949 (this must have been when Alan Turing was there, too). Manchester encoding a 0, uses 0 rising to a 1 in the middle of the bit window and encodes a 1 as a 1 falling to a 0 in the middle of the bit window. There is thus a signal transition in the middle of every bit window so the signal is self-clocking, which is how we can remove the requirement for a scan clock pin. There are also sometimes transitions at bit boundaries which are ignored. Another feature of Manchester encoding is that no matter what the bit sequence, there is no underlying DC current (since every bit is half a zero and half a one). I don't think that this is an advantage in scan test, but it is in networking, and it is a primary reason that the original implementations of Ethernet, the 3Mbps at PARC, the 10Mbps DIX Ethernet (blue book), and the original IEEE 802.3 standard all used Manchester encoding. The underlying medium was coaxial cable and the encoding meant that there was no DC current flowing between transmitting and receiving nodes. Depending on test and functional safety requirements, especially in the context of ISO 26262, this approach can be extended to drive a JTAG TAP controller with full IEEE 1687 (IJTAG) access. This can be used to isolate cores, test memories, and generally do whatever is required, all within the context of just using two pins. The methodology is to develop the tests as if there was full access to the TAP, and when that is complete, migrate the test to use the Manchester encoding and live with just two pins. How well does it work? Normalizing for the fact that Manchester encoding takes two tester cycles per bit, we still end up with results like this: Test approach Normalized Test Time JTAG 4 pin 1004 Manchester 2 pin full scan 1003 Manchester 2 pin compression 209 Combining all the above approaches reduces the test time by over 75% and uses two fewer pins than full JTAG.![]()
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