Virtuosity: Things I Learned in January, February, and March 2016 by Browsing Cadence Online Support

At CDNLive Silicon Valley this month, Cadence announced a new family of ADE tools: Virtuoso ADE Explorer, Assembler, Verifier and VVO (Virtuoso Variation Option). So I'd like to start with a special section highlighting the COS content which will show you all the great new features in those tools. Announcing the new family of ADE tools Rapid Adoption Kits (RAK's) Virtuoso ADE Explorer and ADE Assembler New Features Helps you get started using the new ADE tools and introduces many of the new features, including interactive tuning with Spectre and Run Plans. Run Plan How to use the new Run Plan capability in Virtuoso ADE Assembler to create a sequence of conditional and dependent simulation runs. Advanced Statistical Analysis in Virtuoso ADE Assembler & Virtuoso Variation Option or Virtuoso ADE XL/GXL Creating fast 3-sigma corners to reduce the number of simulations required to achieve the desired circuit yield, setting up and performing circuit optimization over 3-sigma corners and using new fast yield verification methods to validate 3-sigma yield with confidence. Introduction to MAE APIs in Assembler How to use the API's which work with the new maestro database and make it easy to set up customized regression suites. Virtuoso ADE Verifier Introduction to the new tool in the ADE product suite which enables you to perform plan-based analog and mixed signal design verification across an entire design project. Videos Transitioning between ADE Assembler and ADE Explorer This video demonstrates how to transition a test between ADE Assembler and ADE Explorer. In addition, it highlights the important details to be noted during this transition. Migrating ADE L/XL Setup to ADE Assembler This video demonstrates how to migrate an ADE L/ XL Setup to ADE Assembler using GUI and SKILL function Migrating an ADE L Setup to ADE Explorer Demonstrates how to migrate an ADE L setup to ADE Explorer by using the Library Manager, the Loading State form, and SKILL. Getting Started with Virtuoso ADE Explorer This video showcases the graphical-user-interface of ADE Explorer. Also, touches upon its various new features, such as corners, Monte Carlo, checks/asserts, Outputs Setup pane, Results tab, on-demand histories, and so on.. Real Time Tuning with Virtuoso ADE Explorer This video demonstrates the Real Time Tuning feature in ADE Explorer. Virtuoso ADE Verifier Getting Started Overview of the different methods to set up ADE Verifier for analog and mixed-signal design verification. Virtuoso ADE Verifier Basic Flow How to use ADE Verifier for analog and mixed-signal design verification. And now back to your regular programming... Application Notes Dynamic Measurement - Performance Improvement This document explains the performance improvement provided with the Dynamic Measurement feature. Improved Check and Update of CDF Parameters in VLS XL This Application Note explains how you can control which CDF parameters are generated, checked, and updated during layout generation and update. In IC6.1.7, a new list of parameters to check and update has been introduced. ViVA Hints/Tips This presentation outlines some hints, tips and productivity improvements when using ViVA: Annotations/Color, Plotting Saving, Markers, Links. Create Via The document describes new features introduced in Create Via in IC6.1.7 DRE on QT: Enhancements and UI Updates DRE is now on QT, along with this movement there are some usability enhancements and UI updates covered. It is a quick reference document to ramp users on new DRE. Simulating C/C++ Objects with Spectre and AMS Designer This Application Note includes guidelines to run Spectre and AMS Designer (AMSD) simulations using mixed instances of schematic, Verilog-A and C/C++ objects. The C/C++ function call is done from an HDL program compatible to the simulator. Fast Schematic/Symbol Generation using VerilogIn and SpiceIn This documents discusses about the fast schematic generation engine which has been implemented in IC6.1.6.500.10 and onward release. Implementation and Extraction of Thin and Thick Gate Oxides using Abstract Generator This document discusses about the Antenna Effect during the fabrication process. XL Compliance for Analog Layout Automation and Mixed Signal Interoperability This document describes the different XL compliance requirements and provides a way to verify the compliance status to access Analog Automation and Mixed Signal Interoperability. What's New in Virtuoso IC6.1.7 ISR2 Rapid Adoption Kits (RAK's) Virtuoso IPVS This rapid adoption kit is concentrating on helping user ramping up with snapshot based IPVS. Virtuoso Navigator Assistant This RAK steps through the Navigator usage in IC6.1.7 Virtuoso. The objective of this flow is to increase schematic/layout productivity through improved Navigator functionality. Power Managerment Modeling in Electrical & Wreal Verilog-AMS and SystemVerilog Electrical Equivalent using SMG This tutorial covers the different modeling styles for power lines. The classical Verilog-AMS electrical modeling is compared with a Verilog-AMS wreal approach. SystemVerilog with complex data types provides a very attractive alternative in the accuracy or speed tradeoff. In particular for applications, such as power lines where the voltage/current relationship is essential but the complexity of the analog behavior is relatively simple. Clone Constraint In this RAK, we are going to introduce the support of the clone constraint in the constraint manager assistant. Clone feature in Virtuoso XL allows to speed up the layout implementation when a structure, a topology recurs in the design. MODGENs This Rapid Adoption Kit is intended to take you through the steps to use Modgens for Placement and Routing. We will highlight the new features of Modgens in Virtuoso 6.1.7. Videos Browsing Your Code Using SKILL Code Browser This video showcases the capabilities of the SKILL IDE Code Browser. Using the Area and Density Calculator This video describes the Area and Density Calculator feature of VLS L. Configuring IE Card Information Using IE Card Setup After viewing this video, you will be able to setup IE card parameters using the new IE card setup GUI, run the simulation, and verify the results. Highlighting Trunks After viewing this video, you will be able to highlight and view all trunks and the selected trunks along with the twig lines Short Locator in IC617 Virtuoso XL This video will demonstrate the latest Short Locator feature in the IC617 Virtuoso XL Environment. Being a native feature to Virtuoso XL - the user don’t need to invoke external verification tools like PVS - Physical Verification System or Assura, to locate the Power-Signal shorts in the design. The process starts with layout extraction which lists out the shorts in the Annotation Browser; then Short Locator will find the shorts using techniques like Virtual labelling. Getting Started with Symbolic Placement of Devices This video shows how to use Virtuoso Symbolic Placement of Devices to quickly edit selected PMOS and NMOS devices in a design, preview the updates made, and then generate a layout.. Demonstrating Flexible Connectivity Support of Dummy Instances This video demonstrates that dummy instances support flexible connectivity, which means that these instances can acquire the connectivity of the devices that they overlap with.. Using the Net-based Pre-coloring Flow Describes the flow for setting critical nets in schematic that will be routed on the same mask or a specific mask in layout.. Performance and Usability Improvements Parts 1-4 This is a video channel including a detailed series of videos on the new enhancements in VSE and VLS for IC6.1.7. Using the Modgen Editor Assistants This video covers the procedures for performing various tasks using the Modgen Grid Pattern Editor and Grid Pattern Mapping assistants Tips and Tricks: Marker This video demonstrates the various tips, tricks, and shortcuts that you can apply while working with markers in Virtuoso Visualization and Analysis (ViVA). New Training Bytes videos for the following courses Located under Self Learning->Training Bytes Physical Verification System v15.1 Spectre Simulator Fundamentals Virtuoso Spectre Pro SKILL Language Programming Introduction vIC6.1.7 Virtuoso Layout Pro Virtuoso Layout for Advanced Nodes ICADV12.2