FD-SOI: Can I Design It and Manufacture It?

Yesterday I covered the analysis by ARM and VLSI Research on FD-SOI from the symposium held a couple of weeks ago. Today it is the turn of the people who actually manufacture the wafers to bring us up to date on how things are going. First Samsung, and then GLOBALFOUNDRIES. Kelvin Low, Samsung Kelvin summarized the production status of 28 FD-SOI: Technology qualified in 1Q 2015 and is ready for mass production First commercial production started in 1Q 2016 12 product tapeouts in 2015, over 10 planned in 2016 Current tapeouts: network, set-top box (by the way, have you tried putting a set-top box on the top of your TV set recently?), security, gaming, connectivity, AP, ADAS, CIS Future: broader automotive, IoT, wearables, MCU, programmable logic Single platform technology offering (2 Vts, body and gate biasing, overdrive) RF add-on, production PDK by 3Q 2016 eNVM mass production from 2018 Tantalizingly, Kelvin showed a chart of the tapeouts that have happened or are planned. I say tantalizingly, since he said that the colors of the dots represent different market segments, but he wasn't able to give us the key. But you can have some fun guessing anyway. A technology is more than just a process. To be successful as a business there needs to be a good portfolio of IP available. Samsung works with STMicroelectronics (who developed the process and then licensed it to Samsung) for foundation IP, and the two of them work with a range of 3rd party ecosystem partners for advanced IP. But all this is for nothing if the process doesn't yield. They have sucessfully completed qual and are working on automotive Q100 grade 2/3 requirements. There are no fails from SRAM HTOL (after 1000 hours). No fails from environmental tests. The D0 is coming down as planned (although they are not brave enough to put the scale on the vertical axis!) and, as they said earlier, high-volume manufacturing (HVM) has started. Bottom line: it is a real process, you can design in it, there are regular shuttles, HVM has started, D0 is coming down, there is IP support. In the future there will be RF and eNVM options, too. Subi Kengeri, GLOBALFOUNDRIES Subrmani (Subi) Kengeri brought us up to date on the status of 22FDX. He started by listing the foundation IP that is under development (Invecas is their dedicated IP supplier for a lot of this). They also have a full range of interface and other complex IP under development. His tables didn't give availability dates, but since they have been designing test chips with ARM® processors I assume at least a reasonable subset of the foundation IP must be available as a minimum. Subi outlined the future of FDSOI at GF. They have power/performance demonstrated at 14FD with boosters defined down to 10FD. They have already demonstrated SRAM scaling to 7nm (some of the work with CEA-Leti). Subi didn't give details of the timing for bringing up 22FDX manufacturing. From information at previous meetings, I know that the main fab for 22FDX will be the Dresden, Germany one. Obviously, they can also run the process in fab 8 in Malta but that is their main production fab for 14nm (the process shared with Samsung). Cadence It is no good having a great process if there is no EDA flow that works. The big difference between FD-SOI and other processes is the back-bias. This requires a mixture of tool support and design methodology. It is analogous to power supply or clock nets, which are a mixture of chip-level design decisions along with tools that can implement those decisions automatically. The forward and reverse back bias requires additional bias nets which are then attached appropriately to well taps. There are also design rules about how often those well taps need to be inserted, you can't just put a single tap for a huge area. The big test chip that GF did is a quad-core ARM Cortex®-A17 processor. This was divided into five areas (the four cores, and everything else). I actually talked with Jeorg WInkler when he was over from Germany last November. For more details, see How to Do Body Bias with GLOBALFOUNDRIES 22FDX and Innovus Implementation System . All of the Cadence tools required for both custom/analog and digital design, including a complete signoff flow, are now available for FD-SOI (both 22FDX and 28nm) and have been used for production designs at 28nm. The flow is basically the same as any other design with full support for body bias. Previous: FD-SOI: Is it Really a Thing?