As in previous years, a highlight of the Cadence booth at DAC is the theater, where customers and partners (plus the occasional Cadence person) present their experiences with Cadence tools and IP. Presentations take place every half hour (on the hour and half hour) with opportunities to win prizes every hour. The current schedule is in the table below. Where I know something about the subject or the presenter, I've added a bit of color. One other thing about Austin that you may or may not have read about. A couple of weeks ago, the city banned ride-share apps and Uber and Lyft have withdrawn from Austin. They don't want to pay the city $1 per ride. Their drivers don't want to pay the city to be fingerprinted. So you are stuck with taxis. Which really means stuck, since there are not very many of them. 750 apparently. Of course, this is not going down well with the people that used to make extensive use of Uber and Lyft, and especially in the extensive local startup community. As Paul Graham of Y-combinator fame said: "I will go out on a limb and say Austin has zero chance of being a serious startup hub without Uber and Lyft. (I am an investor in neither)." Watch this space. But don't expect normal Bay Area Uber and Lyft service during DAC. Monday 10:00am Cadence Rocketick Introducing RocketSim™: the Fastest Digital Simulator. Just a few weeks ago, Cadence acquired Rocketick. You can read more about it in my post a couple of weeks ago. Presenter is Uri Tal, who was Rocketick's CEO. 10:30am Samsung Samsung Foundry Advanced FinFET Reference Flows with Tool Certifications for Multi-Core Designs. KK Lin, who is in charge of Samsung's foundry design enablement, will present. 11:00am ARM The ARM ® Universe of Models and Its Interoperability with Cadence ® Verification Flows. ARM acquired Carbon Design Systems last year and this presentation is by Bill Neifert, who was the CTO. 11:30am STMicroelectronics TBA, but probably something mixed-signal. 12:00pm ClioSoft Managing AMS Designs for Successful Tapeouts. ClioSoft provides the SOS design management infrastructure, tightly integrated into the Virtuoso environment. 12:30pm ARM Adoption of Genus™ RTL Synthesis Flow on Next-Generation ARM Processors 1:30pm XFAB Don't Screw Up Your Driver! - Simplified Design of Low-RDS on Drivers By Using an Advanced Layout Automation and Verification Flow 2:00pm Samsung Next-Generation P&R Flow Setup by Innovus and 14nm Product Qualification 2:30pm ARM Kickstart Your IoT Design with Cadence and ARM 3:00pm TSMC TSMC-Cadence Collaborations on N10 and N7 Certifications. That's 10nm and 7nm FinFET processes. 3:30pm NXP Tempus™ Concurrent Multi-mode, Multi-corner Analysis at NXP 4:00pm GLOBALFOUNDRIES AMS Reference Flow for GLOBALFOUNDRIES 14nm FinFET Technology. This is the process licensed from Samsung. 4:30pm Cadence Comprehensive SoC Standard Interface Verification. This is about VIP. 5:00pm Texas Instruments Scalable Synthesis: Initial Runtime and QoR Experiences Using Genus Solution 5:30pm ARM Getting a Headstart on Your Artemis/Mimir Implementation Using Cadence Rapid Adoption Kits Tuesday Time Company Presentation Title 10:00am AMLogic Pre-silicon Software Development with Protium™/Palladium ® Environments. Hybrid emulation. 10:30am TowerJazz Hierarchical PCells - For Speed Up of Performance and Disk Space and Memory Usage Reduction 11:00am MIPI MIPI ® Alliance and IP: a Perspective for the Mobile and Mobile-Influenced Markets 11:30am TSMC IP Portfolio for Advanced 16FF+, 10nm and Ultra-Low Power Platform. Libbie Aston presenting. 12:00pm imec Cadence and imec: Partnership to Make 5nm Design a Reality. I was at imec's ITF last week and met Praveen Raghavan, the presenter. 12:30pm Cadence Enabling First-Time Silicon Success with High-Performance DDR IP 1:00pm GLOBALFOUNDRIES Opening a New Dimension in Design with GLOBALFOUNDRIES 22FDX Technology. This is the GF 22nm FD-SOI family of processes. 1:30pm ARM Accelerated System Optimization with CoreLink™ Creator and Interconnect Workbench 2:00pm Vayavya Labs Software-Driven Validation: Using Perspec System Verifier and DDGen 2:30pm Samsung Samsung Foundry 10nm Innovus Enablement and Qualification. KK Lin, who is in charge of Samsung's foundry design enablement, will present. 3:00pm National Instruments Portable Stimulus for Verification and Post-Silicon Test—How to Connect These Two Worlds. George Zafiropoulos, who was the Cadence VP marketing for emulation during my last tour of duty at Cadence, will present 3:30pm GLOBALFOUNDRIES FX-14 Tapeouts Using GLOBALFOUNDRIES ASIC Design Methodology. GF acquired IBM's semiconductor business including the ASIC segment. 4:00pm Teledyne Lecroy Ubiquitous PCI Express Verification from Simulation Thru Post-Silicon Development 4:30pm STMicroelectronics Electrically Aware Design in Smart Power Technologies 5:00pm Surecore Ultra-Low Voltage SRAM: Addressing the Characterization Challenge. Surecore is an IP company based in Sheffield, England (more famous for cutlery). 5:30pm X-FAB Announcing Global MEMS Design Contest. George Cochrane wrote about the contest here Wednesday Time Company Presentation Title 10:00am Adpapt-IP Design and Verification of Flexible 802.11ah Base Band IP Using High-Level Synthesis. Mike McNamara, who used to run the C-to-Silicon product line here at Cadence before leaving to be CEO of Adapt-IP, will present. He presented something similar at CDNLive that I covered here . 10:30am Agnisys Portable Software-Driven Verification 11:00am TSMC TSMC-Cadence Collaborations on N10 and N7 Certifications. Tom Quan will present. 11:30am Cadence 16Gbps High-Speed Interfaces and Beyond 12:00pm Microsemi Evaluation of Perspec System Verifier SW-Driven Test Automation 12:30pm Cadence Accelerating Interface Debugging with Indago Protocol Debug App 1:00pm ARM How ARM and Cadence Partner to Accelerate IoT Design 1:30pm Methodics IP Lifecycle Management - A Superior PLM Experience for Semiconductor Design. Methodics specialize in data management for IP portfolios. 2:00pm Texas Instruments Power Grid Robustness Signoff at the Start of Physical Design Using Voltus™ Effective Resistance Analysis 2:30pm Samsung Foundry Samsung Foundry 10nm Virtuoso Enablement and Qualification. BH Koo will present. 3:00pm GLOBALFOUNDRIES Analog and Mixed-Signal Design with GLOBALFOUNDRIES 22FDX Technology 3:30pm ams International AG Full-Chip EMIR Analysis of Analog-on-Top Designs Using Voltus-Fi and Voltus Tools 4:30pm Cadence Academic Network Announcing Global Tensilica® Design Contest and How Cadence Supports Our University Software Program Members. Yes, in addition to the MEMS contest there is a new Tensilica contest. 5:00pm STMicroelectronics A Better Approach for Today’s Debug Challenges 5:30pm AMD Emulation Productivity: Beyond the Specs This page contains the current up-to-date schedule, but I recommend checking by the Cadence booth at the start of the show to confirm the times of any presentations you especially want to attend. Next: Inside Secure Writes the Book on IoT Security for Dummies Previous: Breakfast Bytes: Post #150![]()
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