Another DAC, and this year someone put a jalapeno in my margarita at the Denali Party . The burn came on slow, and was merciless. So we all yelled “Carpe Diem!” The really good news is that there was a lot of traffic at the floor show, and we seemed to garner the largest crowds. Overall attendance was strong. And we saw increased interest in customers talking with our IP technical experts at the Expert Bar. We shared concepts for selecting the right DDR IP (Figure 1), protocol-level debugging (Figure 2), transaction-level SoC performance analysis (Figure 3), next-generation datacenter equipment architecture (Figure 4), and also discussed an IoT device and system rapid prototyping solution (Figure 5). There are interesting dynamics in the supply of DDR/LPPDR memory chips. And different designs have difference technical requirements, and economics that would impact whether selecting DDR or LPDDR would be best, and which version. Figure 1 supplied the technical background for discussing these points. Figure 1 – Considerations for selecting the right DDR IP One of the biggest challenges for hardware designers and verification engineers is debugging. In particular, once you identify the offending signal, then you need to determine the cause of that error. So Cadence has a protocol abstraction level debugger, the Indago tool, that leverages the knowledge in the Verification IP portfolio to up-level the debug experience. Wow, very cool and very powerful. We used the graphics in Figure 2 to highlight how this debugging would work for the DDR protocol. Figure 2 – Indago protocol abstraction debugging of DDR protocol Another interactive discussion topic used Figure 3 to go into great detail on how transaction-level performance analysis would work for a customer’s SoC. The charts were particularly illustrative of the kinds of micro detail and macro “ah ha!” provided with Verification IP and the Interconnect Workbench. Figure 3 – Transaction-level SoC performance analysis While high-speed DDR remains a crucial technology for every next-generation device, there is no doubt that high-speed SerDes is the hot topic in the industry. Especially when it comes to the revolution happening in datacenters at the hardware level and for software-defined systems. We used Figure 4 for talking points to uncover the customer’s detailed questions and fully discuss the solutions available. Figure 4 – SerDes based IP for next-generation datacenter equipment While some are questioning the real market for IoT chips, there remains strong interest in building these devices. Some people openly questioned why a prototyping board would still be valuable – aren’t all the IoT sensors already built? Yet they acknowledged that IoT software/system prototyping is still important, and probably not all sensor configurations have been built. Figure 5 – ARM’s IoT Prototyping board The good news is there continues to be key technologies driving change in the industry, and Cadence is at the forefront with IP and tools to enable those changes. Steve Brown![]()
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