For all that we’ve heard about the impending demise of Moore’s Law, there is a pipeline full of new materials, device architectures, and techniques that offers promise to further extend semiconductor scaling. That was the takeaway from a “Secrets of Semiconductor Scaling” talk by Dr. An Steegen, EVP of semiconductor technology and systems at imec, on July 13 at Cadence’s San Jose headquarters. Data traffic explosion fueled by internet of things (IoT), mobile, and server applications has created the need for advanced technologies. Designers of these applications are fast adopters. Moore’s Law continues to be necessary, but whether the technology itself can keep pace is the question. “Is there still a way that we can deliver the power, performance, area, and cost in the right combination to make it worthwhile, so that the industry can move to the next node?” Steegen asked. Semiconductor history is marked by periods of “happy scaling” and “dark silicon,” Steegen noted. The 16nm FinFET node is one example where people are pretty happy, she said. But on the other side, there are periods where we haven’t been able to deliver the constant power density needed without having to turn off certain cores in the system. “That’s not what you want to do,” she said. Fortunately, the technology pipeline provides new features to help manage power, performance, and area node by node as we move to the next generation. New features that engineers are working on now are geared toward supporting scaling into future nodes. Toward System Technology Co-Optimization Steegen outlined the different phases of technology development. We’ve moved from a phase centered on lithography, involving novel materials and device architectures, to what is now considered the design technology co-optimization phase. This period is marked by the marriage of circuit enhancement techniques and technology boosters, working together to meet targets for the next node. And some are already thinking ahead about the next phase, system technology co-optimization. Through her talk, she highlighted current and emerging technologies that either are demonstrating the ability to meet power, performance, area, and cost targets, or show promise in doing so: Extreme ultraviolet (EUV) lithography as a single exposure is ideal at 10nm; now that 7nm is knocking on the door, it could be the first node for some foundries to implement EUV In circuit scaling, work is being done on track height library scaling in standard cells. Engineers are researching process features that will enable six-track libraries and, likely, down to 4.5 tracks down the road. Metal patterning options, such as immersion lithography with self-aligned quadruple patterning (SAQP) and EUV (though there are pitch limitations here), are emerging Transistor dimensional scaling involving 3DNAND with layers stacked on top of each other is a trend. Logic (rather than DRAM) is also taking the lead in aggressive dimensional scaling of the features. We’re also seeing more patterning techniques with variations in EUV patterning. Beyond FinFETs, the next device architecture involves nanowires —extremely thin structures with an exceptional length-to-width ratio—to further scale power and performance. Imec has extended simulations to 5nm with nanowires. Copper is being extended with new materials. Cobalt is replacing tungsten in the middle of the line, enhancing resistivity. Cobalt vias help mitigate electromigration. Imec continues to work with Cadence to examine metallization schemes and their impact on circuits. From a system architecture standpoint, neuromorphic computing, tapping into machine learning and deep learning algorithms, offers promise. Typical implementations now include memristors , which are in a development stage. These are just a handful of the emerging technologies and techniques that Steegen highlighted during her talk. She also noted that continued collaboration with companies like Cadence is important for the effort of assessing and validating new technologies. Imec examines device targets and pattern assumptions, for example, while Cadence and its tools “help us digest that information. We funnel this into the development sides of the foundries and fab companies. We make a first assessment of what the features could be. We also validate them,” she explained. Last fall, imec and Cadence announced the tapeout of the first 5nm test chip using EUV and 193 immersion lithography, a milestone that represents the two companies’ dedication and collaborative efforts. There are new ways of thinking that the industry needs to adopt (and adapt to), and there are plenty of other creative ideas in the works to extend semiconductor scaling. That’s good news for a world beyond Moore’s Law. Christine Young![]()
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