Today at the Linley Mobile and Wearables Conference in Santa Clara, Cadence is announcing the latest Tensilica DSP. The Tensilica ® Fusion G3 is a multi-purpose low-power DSP targeted at mobile and other markets. Usually when we design a new processor, it is very focused on a specific application such as audio or wireless basestations. But increasingly there are DSP requirements that are not that specific. At one point it needs to handle the backup camera on a car, and the next it is processing radar. There is also an increasing requirement for floating-point support, removing the need for a lot of complex precision analysis and reprogramming algorithms into fixed point. Another problem with very specialized processors is that there are a limited number of software engineers to do the programming. It is a lot easier if all the processors have the same instruction set and are programmed the same way. Until recently, an SoC would only have one DSP on it, but now there are frequently several, so being able to program them all with the same software development team has become more important. One simplification in programming algorithms is floating point. Instead of detailed analysis of fixed-point precision, just leave it to the hardware. Plus double-precision floating-point when required. With time-to-market demands not getting any more relaxded, the last thing that is needed is for programmers to have to get down to assembly language. These were the drivers of the new Fusion G3 processor. It has very good performance but is not completely focused on a single narrow need. The architecture is balanced with the number of registers, the memory bandwidth, and the processing bandwidth all co-optimized for high performance. In fact, some DSPs have more raw power, measured in MACS, but the Fusion G3 DSP out-performs them in the real world. Other new features are memory protection and integrated DMA. Programming the Fusion G3 DSP uses the same Xtensa Xplorer Ecllipse-based development environment, plus a rich DSP library containing over 550 functions, such as FFT, FIR, IIR, statistics, and more. Full support for 16-bit and 32-bit fixed-point, along with both 32-bit and 64-bit floating-point. So here's the brief summary: High-performance fixed- and floating-point DSP Balanced MAC, load/store, and memory architecture Single- and double-precision vector floating-point Comprehensive data-type support Auto-vectorization for exceptional out-of-the-box performance Easy to port and program in C Based on the proven Xtensa architeture Extensive DSP kernel library Previous: Pathfinding Beyond 5nm![]()
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