By default, the top and bottom stackup layers do not support the placement of embedded components. When an attempt is made to change ‘Embedded Status’ to either ‘Body up’ or ‘Body down’, the system will prompt you accordingly. To help facilitate the requirement for placing components between the top and bottom layers, the 16.6 Allegro PCB Editor release now supports the placing of components directly on the dielectric layer. This requires you to name the dielectric layer(s) prior to invoking the ‘Embedded Layer Setup’ form. Let’s explore a couple of methodologies involving named dielectric(s). Open an Allegro .brd file and then open the cross-section editor - Setup – Cross Section. Enter a name for the dielectric layer; ‘DK_EMB’, for example: Open the Embedded Layer Stackup Form ( Setup – Embedded Layer Setup) and set the ‘Embedded Status’ of the dielectric layer to ‘Body Up’. We will not offer a choice of attach methods: The ‘Embedded_Placement’ property with value of ‘Optional’ has been pre-assigned to the 10 Caps. It’s possible to route on a named dielectric layer. The ‘Allow_Etch’ DRC should be set to ‘False’ to prevent accidental routing from occurring. Set this at the PCSET level: Enter Placement Edit Application mode. Window-select several Caps, then use the RMB – Place on Layer command to drop all components to the dielectric layer (consider using the new 16.6 lasso function to make your selection): Open the Color Dialog – Embedded Geometry folder, noting the subclass structure in place for the named dielectric layer: Let’s assume the routing strategy includes the use of microvias from either surface to the dielectric layer. Open the BB Via form - Setup – BB Via Definitions - Define BB via and enter information as shown in the figure below, then click OK: Ensure the ‘Default’ Physical CSet includes these two vias: Invoke Route – Create Fanout with via direction = ‘via in pad’. Select via BB3-D to connect the 2 pins at the base of the component to the Bottom Layer. Adding a via from the top to the embedded Dk layer will result in a DRC (Via Keepout): Fanout Settings Via in Pad 3-D View Let’s explore an alternative methodology using multiple dielectric layers, as we wish to support the following embedded stackup: Open an Allegro .brd file. Make the following cross-section changes: Add Dk Layer and thickness – ‘DK_EMB1’ = ‘2 mils’ Edit thickness - UNNAMED DIELECTRIC = ‘60 mils’ Add Dk Layer and thickness – ‘DK_EMB2’ = ‘2 mils’ Open the ‘Embedded Layer Setup’ form - Setup – Embedded Layer Setup and enter ‘Body Down’ for DK_EMB1 and ‘Body Up’ for DK_EMB2: The property ‘Embedded Placement’ with the ‘Optional’ value has been pre-assigned to the Caps. Adjust color settings for the two ‘DK_EMB’ layers as you desire: Move the Caps using the RMB – Place on Layer command. Target both dielectric layers for final placement: View the board in 3-D. Enable the visibility of placebounds for Top, Bottom and Embedded Packages. I look forward to your experience using this capability. Jerry “ GenPart ” Grzenia![]()
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