If you design with flash memory components or IP solutions, head on over to the Santa Clara Convention Center to attend the Flash Memory Summit that is being held August 9-11 in Santa Clara, California. Cadence recently announced a partnership with Micron to support Micron’s high-performance, low pin count XTRMFlash interface as part of its controller IP portfolio. This new and faster NOR flash is going to revolutionize the way the industry develops solutions for applications in the automotive, industrial, and consumer industries that demand an “instant-on” performance. Intrigued? Visit us at FMS at booth 614, where Cadence will present our design IP/verification IP solution for Octal SPI interface, along with our solutions for eMMC 5.1 and ONFI 4. Cadence is also presenting our Tensilica processor IP for advanced SSD architectures. With higher efficiency, and virtually unlimited data I/O, designers can simultaneously increase IOPS and consume less energy while retaining the flexibility of a programmable design. Be sure to check out the entire conference program at the conference web site. There are 14 keynote speeches in addition to seminars, forums, and sessions. Online registration is available until August 7, and a free "exhibits and open sessions only" pass gets you into the keynotes and open sessions such as the beer and pizza chat. See you there! Priya Balasubramanian![]()
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