In Game of Thrones , ravens are George RR Martin's way of getting information around faster than a horse, the email of his world. At UC Berkeley, Raven is a RISC-V processor, with an attached vector processing unit, aiming for extreme energy efficiency. And this raven was built using a chisel. Well, with Chisel. First, if you don't yet know about RISC-V then go and read my post about the talk that the professor who led the project gave at DAC. I am convinced that RISC-V is going to be an important instruction set. Soon or later, some big name will build an implementation, either for use in their own datacenters (think Google or Facebook) or as a commercial chip for use in other markets. Just look at the names of the companies that are members of the RISC-V Consortium. I am going to assume that either you already know about RISC-V, or if not that you have read my previous post on the subject. If you don't know about RISC-V, you owe it to yourself to find out at least the basics. At EDPS way back in May, Peter Ateshian from the nearby Monterey Naval Postgraduate School presented the work of a team from Berkeley. He is an alumnus himself and unlike the rest of the team who were at a RISC-V meeting, he was available (not to mention nearby). What is Chisel? It started because UC Berkeley has only a few IC design engineers. But since 10% of Cal’s undergraduates major in computer science these days, there are hundreds of software people available. Instead of using the IC designers to do design, they would train the software people to be “iteration engineers”. Chisel is one of these over-contrived acronyms that stands for Constructing Hardware In Scala Embedded Language. Scala is a software programming language, so when you are writing “Chisel” you are actually writing Scala but with additional class definitions, predefined objects, and usage conventions. The idea is to enable very rapid iteration, “agile” being the term most often used in the software world. The one-sentence takeway is that Chisel is an agile hardware development methodology. Chisel produces Verilog, which can then be run through a standard design flow in the usual way. It is not high-level synthesis (C to gates), it is a hardware construction language. Apparently lines of Verilog itself often map into lines of Chisel almost directly, although obviously there are more powerful constructs in Chisel that do not map directly. It contains concepts including object orientation, functional programming, parameterized types, and type inference. To give you a flavor of Chisel, here is a code fragment: Raven, which was designed using Chisel of course, is a RISC-V vector processor with integrated switched capacitor DC-DC converters and adaptive clocking. The on-chip converters avoid the need for external converters and the adaptive clocking makes the entire chip very low power since almost everything is under dynamic voltage and frequency scaling (DVFS). The goal is extreme energy efficiency. While many production multicore processors achieve coarse-grained power scaling via off-chip regulators, Raven chips employ fast, efficient switched-capacitor DC-DC converters on-chip that allow each voltage area to scale based on its own load. The voltage output of switched-capacitor circuits often has a wide ripple; rather than attempting to filter this ripple, which would decrease conversion efficiency, a clock generator with a fast feedback loop dynamically tracks the ripple, ensuring that each voltage domain is operating at the optimal clock frequency from cycle to cycle. So the Raven project goals were to build a processor that is: Fine-grained DVFS High conversion efficiency Energy efficient (entirely on-chip convertors) Area efficient Low cost The Rocket scalar core, before adding the Hwacha vector support, has a 64-bit 5-stage single-issue in-order pipeline. It has state of the art branch predicition, with a 64-entry branch target buffer (BTB), a 64-entry branch history table (BHT), and a 2-entry return address stack (RAS). Compared to an ARM ® Cortex ® -A5 processor, Rocket gets 1.72DMIPS/MHz versus 1.57DMIPS/MHz, about 10% higher. Without caches, it is 0.14mm versus 0.27mm, so roughly half the size. There have been five 28nm and six 45nm RISC-V chips taped out (as of May). I bet you have a pretty good idea exactly which processes were used, but you would be wrong. The 28nm is ST's FD-SOI technology, and the 45nm is IBM's 45nm SOI technology. Five are various versions of Raven, and six are various versions of another chip called EOS, part of a photonics project. Previous: Breakfast Bytes Guide to Japan Travel![]()
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