SEMICON West runs a sort of award program called Best of the West . Companies submit products, six finalists are chosen, and a final Best of the West is selected. Since SEMICON covers such a wide range, the entries cover everything from wafer processing equipment, to software, to materials. The six finalists get to present their product on the last afternoon of SEMICON. This year the six finalists were: Coventor: SEMulator3D virtual fabrication software CyberOptics: WaferSense and ReticleSense Auto Multi Sensor Graphenea: Graphene Integration on CMOS-Fab Kulicke & Soffa Industries: IConn MEM PLUS High Performance Wire Bonder for Memory Devices Rorze Automation: Rorze N2 Purged LP SPTS Technologies: Rapier-300S The overall winner was Coventor's SEMulator3D. When I worked at SemiWiki, Coventor was one of my clients so I know the product fairly well, and regularly interacted with David Fried, their CTO. Coventor's CEO, Michael Jamiolkowski, accepted the award and then David presented the product. I don't normally write much about other software companies since Cadence has such a broad product line that almost everyone competes with us, so it would be inappropriate. But SEMulator3D is a unique product (and Cadence has been an investor in them since their early days). SEMulator3D fills the gap between early technology development and volume production. For example, 14nm had early papers presenting results in 2011 at conferences like IEDM. Announcements from Intel and Samsung about high-volume manufacturing (HVM) came in 2015. A process technology goes through three phases: research, development, and manufacturing. The early stages can use specialized approaches and can pick just one from a pool of results even if the yield is terrible. But HVM must use scalable approaches, meet a lot of criteria, and account for all variation. Between research and HVM, the historical approach was to build a test chip with characterization structures. Then lots of experimental and split lots would be run and measurements taken. Tweaks would be made to the process about once every one to three months, and more lots run. About once every year or so, a new test chip would be created with updated targets and to address new challenges that had been discovered. This process is getting more and more difficult due to the explosion of process complexity, increased variation due to atomic scale effects and combinations of new elements in the process. These effects pile on each other. For example, multi-patterning doesn't just make the process more complex, it significantly increases the cycle time and thus decreases the number of cycles of learning that can be done in a given amount of time. The solution to this is to use virtual fabrication. Instead of running real wafers, use SEMulator3D to run the process recipe and see the results. It is even possible to run millions of virtually fabricated wafers in a way that would be impossible with a real fab. SEMulator3D basically takes the process recipe and creates a complete model of what structures would be created, that can then be used for visualization and analysis. The first thing that virtual fabrication enables is making the big branch decisions about the process: gate-first, gate-last, FinFET, nMOS first, pMOS first... Variation is an area where virtual fabrication can truly do things that you can't do with real fabrication. It is often the case that "nominal" process specifications yield perfectly, but variation is a known problem. It is time-consuming and expensive to run enough wafers to see the full spectrum of variation, and even then there is never enough area on the test chip to fully observe all the variation. It is always out there, lurking below the surface like an alligator, ready to pounce. Virtual fabrication can also be used for what David calls "back to the well," combining different process elements. One of the first steps of technology development is putting the pieces together, but there are always unexpected interactions. For example, for FinFET there is: Fin—vertical thin-body device, surface treatment, geometry Doping schemes—implant vs solid-source Source/drain engineering—epitaxy, stress, doping Replacement metal gate—deposition process, integration sequence Contact metallization: self-alognment, metallurgy, deposition technique ...and that is just the FEOL The reality of process development is that often it is necessary to go back to the well for more research. Previous: Perspec Modeling![]()
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