The keynote at CDNLive Bengaluru was given by Michal Siwiński. Since day 1 of CDNLive is verification and PCB, and day 2 is digital and analog implementation, almost nobody attends both days. So the keynote was repeated the second day by Vivek Mishra (Michal having already left for CDNLive Shanghai). Major trends such as social, mobile, automotive, and IoT are creating huge opportunities to deliver electronic products. But for a product to be successful, it needs to be differentiated. But products don't live in isolation, devices connect to gateways and up to the cloud. Differentiation comes from optimizing across multiple layers of technology. It is notable, for example, that the top three mobile phone vendors all build their own application processors to control their destiny better. This is a big change. Traditionally standard IP could be assembled to build the hardware, a software stack could be created almost independently, and applications ran in the datacenter. Now the entire stack needs to be optimized together, from the basic silicon structures, up through device software, and all the way into the cloud. Different markets have different requirements. Mobile is critically concerned with battery life. Automotive is very concerned with safety and reliability. Datacenter/cloud is concerned with high performance. Some markets drive the foundry process to the most advanced nodes, others stay back on mainstream nodes such as 28nm or even older. The implementation challenges are different in the most advanced nodes. Advanced nodes care about: New transistors such as FinFET New interconnect layers Multi-patterning and coloring Layout dependent effecets Device variation Complex design rules Whereas mainstream nodes, including older nodes that are being re-engineered especially for low-power, care about: Ultra-low power Mixed signal Advanced packaging Design verification Reliability To build a successful product requires simultaneous optimization of all layers from the end product down the the chip level, and, in the case of some of the most advanced designs, pushing process development. This is what Cadence calls System Design Enablement or SDE. The hardware itself is often implemented as an SoC containing a wide range of IP, complex digital and mixed signal, put in a package with complex power delivery and signal integrity demands, and then on a board with very-high-speed signalling requiring in-depth analysis. IP is actually moving up towards subsystems for things like audio or vision processing. There is a revolution going on in deep learning with changes happening literally every month. The big top-level system development challenges are: Integration: IP. hardware/software, electrical/mechanical Software: Development uses open source tool chains but emulation provides the foundation to verify that the software will run correctly on the chip System analysis: Power, thermal, multi-physics, signal integrity Packaging and board: 2.5D/3D, flex, signal integrity Verification: Hardware/software, IP, SoC, silicon, mixed signal Schedule and manpower: There's never enough of either For a deeper level of details, see the Verification Technology Update and also the section in CDNLive Bengaluru: Day 2 on digital and signoff. Previous: SEMICON Best of the West: Coventor![]()
![]()
↧