I had an exciting week in July here in Pittsburgh, PA with the IEEE Computer Society Annual Symposium on VLSI ( ISVLSI.org ). I was fortunate enough to be invited to do one of the keynotes at the Symposium, thanks to the co-chairs: University of Pittsburgh Professor Helen Li and Carnegie Mellon University Professor Xin Li, and my connection to them through the Cadence Academic Network and Cadence Director Patrick Haspel. My normal day as an engineering director in Virtuoso R&D focuses on ensuring our continued incremental and innovative progress in assisted and automated placement and routing for our customers. So taking a few days out to see where the academic research and attention is focused was really enjoyable. There was great diversity at the symposium with attendees from all over the globe and working on many different topics. The variety of topics for the keynotes and panels was really interesting: Dr. Sani Nassif talked about his experience moving from IBM to founding a company (Radyalis LLC) to apply EDA algorithms to the aiming of X-rays to kill cancer cells in the health industry. Dr. Martin Wong gave a very interesting talk on EDA algorithms to attack many of the complex advanced-node DFM challenges such as SADP, MPT, and E-beam lithography. I talked about the design implications on analog and custom design for advanced-node layout, specifically due to the challenges of FinFETs, SADP-routing layers, layout dependent effects, and density gradient requirements. Xianfeng (Sean) Ding of Huawei talked about Huawei's goals and needs around IoT and sensors, and reviewed a number of IoT and wearable trends. The lunch panel on "Nanotechnology-Inspired Future Computing, Challenges and Opportunities" which reviewed the Q4-2015 announced US-government-backed Grand Challenges and strategic initiatives. The panelists were all from various funding and research agencies (NSF, DARPA, NSA, DOE, Oak Ridge National Laboratory, and Air Force Research Lab). The panel was basically presenting their views on how to best take the high-level goals and vision of these initiatives (best summarized here and here ) and turn them in to specific areas of research and development. There was a lot of interesting discussion about the "'what" and "why" of 'brain-inspired computing architectures. Beyond the keynotes and panels, it was clear that the focus of the interesting papers and research was in two non-traditional areas: Nano-scale/post-CMOS devices and non-Von Neumann architectures: A lot of papers on memristors and the type of innovative circuit architectures that could be created with them, as well as other technologies and layer stacks applied to FinFETs to address power and performance. Many talks on "brain-inspired computing" design. There was a great talk by Dr. Catherin Schuman on this topic. Similar slides to what she presented at ISVLSI can be found here . Finally, I was most gratified to have a detailed discussion about how professors and their graduate students are using Virtuoso today, and the need for generic process design kits [GPDKs] for both teaching and research. I was happy to be able to point them to the most recent GPDK release with FinFET enablement in gpdk_ff. It was a great opportunity to interact with the academic community, and I look forward to the next opportunity.![]()
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