At CDNLive in India, Cadence's Hany Elhak discussed aging and self-heating, and how to analyze it. All transistors age and all transistors have self-heating effects. However, aging wasn't really an issue until 28nm. 90nm transistors will last essentially forever. Planar transistors didn't suffer much from self-heating either, the topology and size of the transistor meant that the heat could escape and the interconnect acted as a sort of heat sink. But with FinFETs, self heating has become a real issue. Aging effects are really divided into three different periods. In the early stage of the device there can be early-stage failure, opens and shorts, excessive leakage. If the device survives infant mortality, then there can be occasional random failures. Eventually the devices wear out and there start to be new types of failure from hot carrier injection, metal migration, dielectric breakdown. Also, the performance will gradually degrade, which is a big problem for analog designs. It is actually somewhat of a misnomer to call it aging, which implies it is just a matter of time, but it actually happens because of electrical stress. If the device is powered down, then it is not aging. The self-heating effects interact with aging, accelerating it. With FinFETs the thermal effects get worse. The gates are shorter and the narrow fins have lower thermal connectivity. Also, FinFETs are higher powered devices, which also increases the channel temperature. It is necessary to use simulation to calculate the temperature rise. This doesn't just affect performance but also reliability (e.g. electromigration is worse at higher temperatures). Unfortunately there is a positive feedback loop. One way to do this is to turn on self-heating analysis and apply the setting, shmod=1. But this adds an extra node to every device, so with 5M devices, that is 5M extra nodes which can lead to performance problems and convergence problems. Every time step, the simulator is evaluating not just the current flow but the thermal flow. However, in reality, temperatures only change slowly, so this approach is overkill in some ways. A better approach is to switch to a two-step flow. A first nominal simulation is used to calculate the device temperatures (without taking the effect of temperature on performance into account). Then, a second simulation is done using the temperatures calculated in the first simulation. This process can actually be iterated more than twice for greater accuracy if necessary. The big advantage of this approach is that not updating the device temperature on each time step speeds up performance. It almost eliminates non-convergence issues due to the added thermal nodes, and the model can consider not just the temperature effects of a given device but also the effect of adjacent devices. Reliability analysis works in a similar manner. A first simulation works out how things like Vt have been impacted. This is used to update the models in the netlist and then a second simulation is done with aged models to see how the devices will work after 1 year, 3 years, 10 years, etc. These two two-step approaches for aging and for self-heating can be combined: Calculate the device temperatures by simulating the fresh circuit Stress the devices, and calculate the degradation under the elevated temperature Aged devices consider the raised temperature This approach is supported in the Virtuoso ADE flow. In fact, the simulator checks whether self-heating or aging models are present and so automatically will do self-heating only or aging only if one model is missing. In a Xilinx presentation at CDNLive in Silicon Valley, they did a more in-depth analysis and concluded that ignoring self-heating when analyzing device aging leads to serious reliability issues. There are plenty of detailed tables and graphs at the link. Previous: Piloted Driving: Audi's View![]()
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