Twice a year TSMC has a big meeting in San Jose. These are the times that there is a public update on their process roadmap, how process ramps are going, the OIP ecosystem, and so on. But they make it hard for people like me since their rules are that they won't hand out the presentations, they won't let you take pictures of the screen, they won't let you video or record the presentations. But I'm allowed to take away anything that I can write down. Inevitably there are probably minor errors. So if you are wondering why this is so sparsely illustrated, that's the reason. There were two presentations, one from Jack Sun on process technology and one from Cliff Hou on design technology Here's my summary of what they said. Jack Sun Jack started by saying he would talk about three things: 3D logic technology ULP and specialty processes for IoT 3D wafer-level system integration technology The other aspect of the TSMC roadmap, that they announced early this year, was that their singular focus is no longer mobile. Yes, they will still lead with mobile at advanced nodes driven by the usual suspects. But they are now having a complete ecosystem, including specialized processes, for high-performance computing (HPC), automotive and IoT. The basic technology roadmap is 2D pitch scaling (in the past), 3D FinFET and 3D memory (today), and gate-all-around (GAA) nanowire FET in the future. I have never heard anyone at TSMC acknowledge any competition before, but Jack said that compared to FD-SOI FinFET allows a much lower operating voltage. The process roadmap at the detailed level is complex. In the past there were 28LP, 28HPM, 28HPC, and 16FF+. This year they started volume production of 16FFC which is a compact version of 16FF+, with special platforms for IoT and automotive available (high performance computing is expected to remain on the higher performance 16FF+ process). N10 is now qualified for production ramp. N7 is on track with good yield, planned Q1 2017 risk production (256Mb SRAM yield is ahead of plan, he showed some graphs but I'm not allowed to take pictures remember). There are already over 20 customers with multiple tapeouts planned for 2Q 2017 onwards. How good is 10nm? There is a 50% die scaling, 50% speed gain (or 40% power reduction at the same performance). This is compared to 16nm. There are 3 Vts and gate-lengths to cover a wide range of speed versus leakage tradeoffs. And N7 coming with15-20% speed improvement, or 35-40% power, and about 1.63X routed gate density Looking to the future, it is all about new structures and new materials: Ge FinFET III-V FinFet III-V GAA FET stacked GAA nanowire FET tunnel FET ("the holy grail") graphene nano ribbon and carbon nanotube FET One big area of interest is EUV. TSMC have "seen" 125W power (which I think means that ASML have demonstrated that but the scanners installed at TSMC don't have that power source yet). The goal remains 250W. Reliability in terms of up-time are getting there. On 3 consecutive days, for example, TSMC manufactured 1458, 1633 and 1556 wafers. There are also advances in the other gotchas in the EUV ecosystem: reducing native defects on mask blanks, pellicle readiness, and resist sensitivity with good line width control. Jack then moved on toe ULP and specialty IoT processes. TSMC has processes for MEMS, CMOS image sensor (CIS), eFlash, RF, logic (duh), analog, high voltage, eDRAM and BCD-power. There are specialized low power processes previously announced: 55ULP (ultra low power), 40ULP, 28HPC+, 16FFC. Low leakage SRAM cell for lower retention leakage during standby (IoT devices spend a lot of time doing nothing). They have the "most advanced" eNVM technology. N40LP eFlash started entered production in 2015. N28 eFlash is under development. Also emerging memory technologies eRRAM and eMRAM (these are built in the metal stack, not on the base wafer). eRRAM is positioned as an eFlash alternative for MCU, eMRAM is positioned as an eFlash and eRAM alternative for MCU, last-level cache, eDRAM replacement with lower latency and low power. TSMC is on their 3rd generation of power devices BCD and NLDMOS, 24V, 12V and 5V. They also have GaN on silicon power technology, which is CMOS compatible. Very low on-resistance with high breakdown voltage (40V, 100V and (wow) 650V). 100V and 650V have passed industrial reliability qualification. For automotive logic technology, ADAS is going down to 10/7nm since it needs lots of processing power for all those cameras and radar units. For CIS, it was front-side, now back-side (this means that the die is flipped and light goes through the silicon to get to the photoreceptors, the CIS is directly attached to the logic underneath without requiring TSVs), now backside with ISP stack, and near-infra-red (NIR). Finally, Jack's third topic was wafer level system integration. TSMC has two main 3D integration systems: CoWoS (chip on wafer on substrate): this is a silicon interposer technology for high performance at a cost, in production since 2012 (most famously with Xilinx's very high end arrays) InFO (integrated fan out): this is a low cost consumer-oriented technology with small form factor that came into production this year (yes, your new phone probably contains some). The vertical stack is less than 1mm. InFO POP is logic with DRAM on top, 15mmx15mm package, 300um PoP/TIV pitch, 3RDL routing layers, 10um pitch with integrated passive devices (decaps) for optimized power delivery. Coming soon, InFO multi-die (side-by-side die) with 3 layes of 2um fine pitch RDL. NVIDIA has a part in production with a logic chip and a 4 die HBM stack. They also have wafer on wafer bonding, but Jack only spent a moment on it and I'm not quite sure where it fits in with everything else. Summary: motherhood and AP (apple pie, not application processors), 3D transistors, 3D system integration ("don't think of it as conventional test and assembly"). Focus on mobile, HPC, automotive and IoT. Cliff Hou Cliff talked about the ecosystem around the process. Since TSMC's strategy is joined-up, you won't be surprised to know which four areas they are focused on in the ecosystem: mobile: continue to drive sped, power and area HPC: sustainable performance, memory bandwidth, reliability automotive: reliability, functional safety, standard compliance. 16FFC to meet auto grade IoT: ultra low power It is not just a process, as Cliff pointed out. A design enablement platform needs: reference subsystems processor cores standard IP (meaning things like USB, DDR, Ethernet) foundation IP (standard cells, memories) EDA flows specialized process options (sometimes) For years, TSMC has used ARM ® processors as a process driver for logic. They had the first 2GHz core in N20SOC, 64-bit big.LITTLE processors at 2.5GHz in 16FF, 64-bit generation in N10 (see a future blog post with some details on how ARM, TSMC and Cadence worked together on this), optimized ARM Cortex ® -A73 solution for 16FFC, pushing up to 4GHz for HPC in N7. So what is the status of each of the various platforms? Mobile design enablement platform status: 28HPC, 16FFC, 10FF all in production with 7FF design ready (V0.5). 7nm standard cells versus 28nm have 6X the density, 2X the performance per watt, GPIO about 3X scaling. 7nm SRAM has 4X scaling and adding new ultra-high-density compilers. Standard cell and memory silicon validated, all the memory compilers taping out in November with silicon validation by end of Q1 2017. ARM A72 has either 30% performance improvement or 56% power reduction. InFO integrated database for physical verification and electrical analysis (in particular, integrated analysis to find the "real" thermal hot spots after assembly, which might not be where they show up on individual die analyzed separately) HPC design enablement platform (on N7 for datacenter): FEOL overdrive, BEOL wide metal, large via, via pillar. H360 standard cell library. L1 cache macros. L2/L3 cache macros (December). High speed SerDes at 56G and 100G (Q2 2017). N7 with H360 can reach 4GHz. HPC re-uses most IP apart from these Automotive design enablement platform: ISO26262 ASIL-B certified foundation IP, DRC/LVS enhancements for automotive reliability, EM rules, enhance reliability from consumer grade to auto grade (in particular 150 ° C, aging models, AEC-Q100 qualification). SRAM validated IoT design enablement platform: ULP near -Vt under evaluation. But amplifies variation at corners, so need tighter process control and special bit cells, along with some changes to foundation IP to mitigate variation. Design flow needs enhancement in variation modeling and STA accuracy. Already have N7 IoT offering (V0.5) for high-end wearables The summary: mobile: in production since, like, forever HPC for 16FF+ in production, 7nm ready for design start automotive on 16FFC ready for design start, 7nm coming IoT in production for 90nm, 55ULP, 40ULP, 28PHC+. 16FFC and 7nm ready for design start Next update: week of 14th March 2017. I'll be there for you. Previous: System Design Enablement with Cadence and TSMC![]()
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