There are different conferences on microelectronics. There are the industry conferences, where the CEOs are telling how well their companies are prepared for or against the next disruption, these conferences have usually the best food. Then there are big academic conferences, where professors from all other the world are meeting (the food is still good) and smaller academic conferences, where PhD students are presenting their papers (here the food is worse). Then there is CDNLive EMEA , the only conference I saw people dancing (the quality of food may vary), and then there are activist conferences like ORCONF . The entrance is for free, for the dinner people are paying themselves, but this year the conference found place in Bologna, Italy, and the food cannot be bad in Italy. However, ORCONF is one of the most exciting conferences, I’ve visited this year, people there really love what they are doing. It is not about getting a degree or publishing a paper, it is about presenting their work and their efforts to the community, and receiving deserved respect for this. The “OR” in ORCONF stands for OpenRISC , an open-sources processor IP, which is licensed under GPL. This was the fourth conference, the first one started as pure OpenRISC community conference, but in the meantime other processor architectures, like RISC V , get more attention, so only very few presentations were about OpenRISC, but quite many about RISC V. OpenRISC is an older architecture, but RISC V ISA is licensed under BSD license, which might explain, why RISC V gets more attention from the industry. More than 15 attendees were from ETH Zurich and Bologna University, Professor Davide Rossi did an extensive presentation of the PULP processor, which in its current status is an implementation of the RISC V ISA. There is already an ecosystem in development around this processor, the company Greenwaves is announcing an IoT SoC, which will include a PULP core, while the lowRISC processor will use stripped-down PULP version called Pulpino for programmable IO-interfaces. Professor Elkim Roa from Universidad Industrial de Santander, Columbia, presented the world’s first silicon implementation of RISC V processor in TSMC 130 technology. And OpenPiton is open-source manycores, multithreaded design, which has been taped out in IBM 32nm technology. It consists of 25 cores and is one of the largest academic designs build so far. But also software aspects have been discussed. New generation of hardware descriptions languages as Chisel and FIRRTL -based flow (FIRRTL stands for Flexible IR for RTL), which compiles object-oriented Chisel into Verilog builds a bridge for software-developers towards hardware design. Mihai Lazarescu from Torino University presented an approach on how to convert OpenCL based software into SystemC, which then can be synthesized by HLS tool for FPGA. The results for some algorithms, which can be used in deep-learning algorithms, are stunning, the energy consumption is orders of magnitude lower compared to GP GPUs, which are currently used for the job. One important announcement is the start of the LibreCores platform. Everyone involved in IP design may know the OpenCores website, which is dedicated to collect open source IP for more than 14 years now, but unfortunately due to financial situation of the company, which was supporting OpenCores, the development and the support of this website has been ceased. So activists like Stefan Wallentowitz decided to establish the FOSSI foundation, which has launched LibreCores. Functionality of the platform is quite basic right now, but there are big plans how to support developers of Open Hardware IP, especially in the area of continuous integration and verification, if their IP is properly working on different FPGA boards. So in summary I can state, that ORCONF is a real jewel among microelectronics conferences, and while the community is obviously smaller than the open-source software community, it has phenomenal spirit and bold ideas. To learn more, view the video recordings of the conference .![]()
![]()
↧