The fifth (V th ?) RISC-V workshop took place this week at Google in Mountain View. This was actually the third workshop this year. Rick O'Connor, the executive director of the RISC-V foundation, opened the meeting. "It's been quite a year," he said, giving the statistics. At the workshop, there were 350 attendees (up over 100 since the workshop in July), who represented 107 companies and 30 universities. There were actually too many people to fit into the lecture theater at Google, and so there was also an overflow room with a video feed. RISC-V Momentum From talking to people in the breaks, it is clear that RISC-V is completely dominant in academia for things requiring an ISA such as building chips, compilers, and so on. Dave Patterson of UC Berkeley (and Google) stepped up to the microphone at one of the Q&As. Just in case you don't know who he is, he created the first Berkeley RISC architecture (of which RISC-V is the fifth in the series) and, along with John Hennessey of Stanford and MIPS fame, wrote the standard text Computer Architecture: A Quantitative Approach . In fact, Dave said that the next edition (which should come out in about May next year) will be RISC-V based, as will the next edition of Computer Organization and Design . He gave his view on why there has been such a strong reaction to RISC-V. He pointed out that lots of customers are getting nervous about ARM from both pricing and accessibility (for academia). The first decision when building any SoC is to pick the processor. RISC-V, being available from more sources all the time, means that the decision can be made early and the exact details nailed down later. "You can pick an instruction set without tying yourself to a company." Another interesting sign of growing interest in RISC-V is that Codasip's RISC-V processor has been the most popular IP on Design & Reuse's website for the last three weeks (and, off this topic, the second most popular is Cadence's automotive Ethernet MAC). There were several different types of presentations at the workshop. They ranged from experience with general software solutions that could run on any architecture, to very specific software for some aspect of RISC-V. I will focus on the people who discussed semiconductor implementations and flows, since I think in the long run these are the most important from a commercial point of view. Ultimately, if RISC-V is going to change the world, it will need to get into a large number of chips. SiFive SiFive announced the first commercially available RISC-V SoC implementation, the Freedom E310. I'll write about this in detail, including my talk with Jack Kang, next week. One especially noteworthy aspect of the announcement was that they open-sourced the RTL for the SoC. I can't think of any other commercial chip design where the source code is also available freely. Codasip As I said above, Codasip's implementation has been the top of the D&R hit parade for the last three weeks. Neil Hand, VP marketing, explained the details. I will cover their approach in more detail in a later post. Go for RISC-V "Go for RISC-V" sounds like some sort of advertising slogan, but in fact Go is a programming language invented by a company whose name starts "Go", namely Google. It is open-sourced, so there are many other contributors, but I gather that Go is extensively used within Google. Benjamin Barenblat and Michael Pratt presented some details of their experience of porting Go to RISC-V. One immediate question that occurred to many people was what the significance of this was, and somebody asked during the Q&A. The presenters said that it is "just Google investing in alternative ISAs." But then they would say that, so we still don't know if Google is doing anything significant with RISC-V. Security Keynote Eric Grosse of Google Security ("Not the guys in the blue shirts making sure you don't wander off around the campus.") gave a fascinating talk about Google's approach to security. He started off saying that you need to know your adversary. He learned a lot during the December 2009 incident with China. And Rowhammer in 2014. And the great BIOS lockdown of 2011, which nobody in the audience appeared to have heard about, it was quietly handled without incident. When his slides or the video is available I will merge with my notes in a separate post. Most of his talk was not especially RISC-V specific, but he did have a message for everyone there: You have the critical advantage of openness, be sure to keep it Resist adding features lightly Consider CHERI security extension Another advantage of RISC-V came out in the questions, too. Someone asked how Google (or anyone) can be sure Intel isn't putting stuff into the x86 chips (or someone other than Intel). Eric said that he was pretty sure that wasn't happening, but that having an open implementation, with multiple companies supplying chips, was even better. Open Source Hardware Several presenters pointed out that with Moore's Law ending, the time is now for open-source hardware. Design starts are up about 10% in non-leading-edge processes. In particular IoT designs mostly do not require advanced nodes. The ease of integration of analog and perhaps some sensors is more important. Another common thread about the teams doing design of RISC-V implementation in silicon is that everyone seems to be using Chisel. This is a Berkeley language that is an extension of the Scala programming language with the aim of making chip design possible with a team consisting of lots of computer scientists and very few IC designers. The original motivation being that Berkeley undergraduate population is like that, with 10% of Berkeley's intake being CS majors, and relatively few EE majors among them, a pattern that also continues up into postgrads and probably higher, too. You can read more about Chisel in my post A Raven has Landed: RISC-V and Chisel . 6 th RISC-V Workshop The sixth RISC-V workshop will be May 9-10 in Shanghai, hosted by NVIDIA and Jiao Tong University. The seventh workshop will be late in 2017 somewhere in Silicon Valley. Previous: The Internet of Space![]()
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