The Sunday of IEDM there were two all-day short courses. The one I attended was Technology Options for the 5nm Node . It was organized by An Steegen of imec. I am not going to attempt to cover the entire day's presentations in a short post like this, but the topics covered included lithography, channel materials, transistor options beyond FinFET, low-resistance contacts, minimizing parasitics in the metal stack, and metrology. This all takes place against a background that An described as "dimensional scaling under pressure" and others have described as the end of Moore's Law. See the diagram above—true "happy scaling" Moore's Law is the grey line and we are clearly falling below that. It is expected that 5nm will be available in 2020, which is only four years away. The EUV story has not settled down and so 5nm has to be developed without assuming EUV will be ready for high-volume manufacturing, but also acknowledging that it might come along as a cost reduction. But nobody is going to risk designing a process that assumes EUV and has tolerances that cannot be achieved with LEx or SAxP lithography. Last year at IEDM, there was an earlier session on 5nm. There were lots of academics presenting novel architectures for both transistors and interconnect. Then two sessions with industry veterans dismissed all of them as needing at least a decade to get from the lab to high-volume manufacturing, and thus too late to be ready in time. See 5nm: Academics and Industry Examine the Options . The conclusions then were: Transistors will be either FinFET or multiple silicon nanotube gates. Vertical nanotubes or other esoteric technologies will not happen in this time frame. Interconnect will be copper, but resistance is a big issue. Carbon nanotubes and on-chip optical interconnect will not happen in this timeframe. Had anything changed this year? At the press lunch, IEDM said that they deliberately kept out the "academics like me, since we all think everything is good." So it was mostly people from industry with people from Tokyo Electron, Lam Research, IBM, Applied Materials, and imec. Academia was represented by the University of Singapore. Well, there seem to be three key decisions that need to be made for a successful 5nm process: Transistor architecture: FinFET or something else Interconnect: copper or something else Contact: how to get resistance down FEOL: Transistor Architecture The conservative approach is to carry on pushing FinFET as long as possible. Something that is not too different are horizontal gate all around nanowires, where the fin is basically broken up into multiple wires (at least three or a fin is probably better). Strain engineering will continue to be a tool to get mobility up, but the transistors will probably need SiGe or additional III-V materials added, too. The less-conservative approach, but still involving only techniques that are already mastered, is gate all around nanowires (see picture above). This example shows two wires, but I have also heard that unless you do three or more, the drive is less than you get with FinFET so there is little point in the added manufacturing complexity. Beyond that, there are many options for new types of device (see the above chart). The two most promising technologies seem to be TFET (tunelling FET) and Neg-Cg FET (negative gate capacitance FET). These both get past the 60mV/decade limitation of silicon as a channel material. We have successfully manufactured TFETs, but the tolerance required for high-yield manufacturing is challenging and may not be achievable in high volume. They have a very steep sub-threshold slope giving scope for tradeoff between V t and I off . The other promising technology is the negative-capacitance gate FET. I confess I don't entirely understand this. The capacitor seems to be formed from a ferroelectric capacitor in series with a metal gate capacitor, which gives built-in voltage gain. Here are all the technologies in a table with the tradeoffs and readiness: So the conclusion: 5nm will be a variety of FinFET, with taller thinner fins. There is a small chance for horizontal gate all around nanowires (GAANW). BEOL: Contacts There are two big issues with contacts. One is developing a self-aligned contact (SAC) for the lowest levels. The contacted poly to gate pitch (along with metal2) is one of the most critical measurements for how small standard cells can be drawn and manufactured, and thus how much the area shrinks in practice. There are a number of different approaches to manufacturing the SAC. The above diagrams come from Intel. The second problem is the liner. Contact have recently been made from copper or tungsten. But copper/tungsten is too dangerous to let anywhere near the transistors and so the contact hole is first filled with a liner. Then the liner is filled with copper. The problem is that the liner thickness does not scale with the process. Since the liner materials (TaN etc) are high resistance, as the technology node shrinks, more and more of the resistance is due to the liner across the bottom of the contact hole, through which all the current has to flow. One solution that is looking increasingly attractive is to use cobalt in combination with other materials for both the liner and the contact fill, as in the above diagram. In interconnect, as the process scales, the length of metal shrinks but the number of vias remains the same. Since their resistance is not decreasing much, the fraction of resistance due to contact/via is increasing. So that is the reason that reducing contact resistance has become so important. Conclusion: It looks increasingly likely that cobalt and copper or titanium (or both) will form the basis of contacts. BEOL: Metalization The challenge with interconnect is that resistance goes up as the wires get thinner. Obviously if the wires are made thicker there are two negatives: they take up more space, potentially increasing area and cost, and they increase capacitance. As a result, simply scaling from 7nm to 5nm is unattractive. One change is asymmetric width and spacing, making the wire wider (to reduce resistance at a small increase in capacitance). Another relatively straightforward change is adding air gaps instead of dielectric, increasing performance without adding any new materials. There is some scope for new materials such as Co,Ru,Rh,Ir,Mo,or Ni. These are likely to show up in MOL interconnect first, but for now they are not as good as copper. Conclusion: 5nm interconnect will be copper based, with different liners (probably) and airgaps. Summary FinFET, copper interconnect, new contact liners: lots of detailed incremental engineering to make all this work and yield in volume. Previous: RISC-V Available in Silicon![]()
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