At IEDM last week, there were papers in eight parallel tracks for three days. At the end of session #2, on the first day, there were two "late" papers by TSMC and by the consortium of IBM, GLOBALFOUNDRIES, and Samsung talking about 7nm. TSMC Michael Wu of TSMC presented a paper that had over 30 authors. The title was A 7nm CMOS Platform Technology Featuring 4th Generation FinFET Transistors with a 0.027um2 High Density 6-T SRAM Cell for Mobile SoC Applications . Michael compared the technology to 16FF+, not to 10nm. In the Q&A at the end, someone asked about this and Michael gave the undoubtedly true answer that 10nm was between the two. Some key points: Over 3.3X routed gate density improvement (compared to 16FF+) 40% speed gain or a power reduction of over 65% Improved electrostatics due to the fin profile (in the Q&A, Michael said that the aspect ratio was more than 10) Fully functional 256Mb SRAM with cell size of 0.027um2 (operates down to 0.5V) Multi-Vt device options for low-power and high-performance design requirements Drive current boost 30% for nmos and 40% for pmos Reduced gate resistance due to reduced thermal noise The FEOL is a 4th generation FinFET. The BEOL has m0/m1 with tight distribution of metal resistance. There is a 12-level metal stack, m0-m4 are 1X, m5-m9 are 1.9X, and m10+ are thick metal. There are two test chips. The SRAM test chip, which is 256Mb. The density increase is 2.6X (again versus 16FF+) and performance increase as much as 80% at some voltages. The logic test chip has a CPU and a GPU. Since the CPU is an ARM ® Cortex ® -A72 processor, I assume the GPU is a flavor of ARM's Mali. The 7nm process achieves NMOS TDDB and PMOS NBTI lifetimes comparable to 16FF+, using careful post high-k/MG thermal optimization. In addition, I/O devices are also optimized by junction doping profile to reduce S/D to substrate leakage current and hence enhance hot carrier immunity. The test chips were all fabricated using 193i lithography, but they are working on EUV, too. In the Q&A, Michael was asked whether EUV was just a test vehicle at 7nm and he said it was. I take that to mean that TSMC will introduce 7nm without EUV, reserving it as a possible cost-reducer if and when it works in HVM. IBM, GLOBALFOUNDRIES, Samsung Not to be outdone on the author count front, the 7nm joint paper by IBM, GLOBALFOUNDRIES, and Samsung had more like 60 authors. Huiming Bu of IBM actually presented the work. Since the three companies work together only precompetitively, as far as I know (except that GLOBALFOUNDRIES licenses Samsung's 14nm process), this may be more of a research paper and doesn't necessarily represent all the details of either GLOBALFOUNDRIES or Samsung's eventual production process (of course, IBM no longer has a production process, having sold that business to GLOBALFOUNDRIES, but they still do semiconductor research). However, I said that to someone who works for one of the three companies and they told me not to underestimate the paper, so...don't underestimate the paper. The paper compared 7nm to a 10nm reference point: Fin pitch reduced from 42 to 27 Contacted poly pitch reduced from 64 to 44/48 Metal pitch reduced from 48 to 36 The process flow, based on replacement metal gate (RMG) and self-aligned contact (SAC), is shown above. It features dual strained channels on a thick strain relaxed buffer (SRB) virtual substrate with a super steep retrograde well (SSRW) to enhance the channel mobility for both NFET and PFET. During the Q&A, he was asked about the thickness of the SRB but declined to comment. A schematic view is shown below: There is a second-generation self-aligned contact (SAC) and cobalt MOL. There is new metal for resistance reduction (not sure if that is different from the cobalt MOL or just another description of the same thing). In the Q&A, Huiming was asked about EUV, whether it was essential or just nice to have. He said he was sure they could do the same with immersion, meaning that the design rules clearly don't depend on EUV as the light source. He was also asked about SRAM yield, but since the process was not yet mature, he didn't have good numbers yet. Previous: Tensilica at CES: Hololens Will Be There, Will You?![]()
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