BREAKING NEWS: I just received an email that the panel I wrote about at ESD Alliance Panel on Energy Policy for the IoT Era has been postponed to a later date due to "unforeseen circumstances." I don't know any more than that, but don't turn up at City Hall on March 23rd. Yes, it's that time of year again. Just like a cat has nine lives, Cadence has nine CDNLives. They will take place all over the world through the year. Click on the map for more details. CDNLive kicks off in Silicon Valley April 11-12th at the Santa Clara Convention Center. The day will open with a keynote from Kushagra Vaid, who is GM of Azure Hardware Infrastructure at Microsoft. Azure is the name of Microsoft's collection of cloud services, the fastest-growing major part of their business. Prior to Microsoft, Kushagra spent a decade at Intel where he started as a design engineer and rose to become Principal Engineer, responsible for driving the technology direction of Intel’s Xeon microprocessors. Kushagra has been instrumental in driving Microsoft’s success as a leading hyperscale cloud operator and is a recognized industry leader in Open Source hardware. He and his team have successfully delivered three generations of cloud hardware, deployed at a massive scale across a global fleet of datacenters. Lip-Bu Tan, the Cadence CEO, will give the second keynote. I've not seen a title but I'm assuming that he will give an update on the overall company and a perspective on Cadence's System Design Enablement (SDE) strategy. The fastest growing part of Cadence's business is not the traditional semiconductor companies but system companies. It is not a coincidence that the top three smartphone vendors (Apple, Samsung, and Huawei/HiSilicon) all design their own chips, recently joined by Xiaomi. Automotive manufacturers and their tier-1 suppliers are starting to move in the same direction. An optimal system requires software, chips, packages and boards to be designed together. The third keynote will be by Anirudh Devgan, Executive VP of DSG and SVG. Since that won't mean much if you are not immersed in Cadence acronyms, that means he is in charge of digital and verification, including VIP. I know what he will be talking about but it is not yet public. Be sure to be there and be one of the first to find out. As usual, the focus of CDNLive is on our customers. Typically, over 2/3 of the presentations are by customers of Cadence, with the remainder by Cadence staff giving a deeper perspective and an outlook for the future of the various areas where Cadence supplies products. After that, the day will follow a similar format to previous years, with multiple parallel sessions. The tracks are: Academic (Cadence Academic Network) Custom / Advanced Node Digital Implementation / Advanced Node Front-end Design IP and Block Verification Mixed signal and Low Power PCB Design PCB Simulation Signoff SoC and System Verification Tensilica and Design IP Details about CDNLive Silicon Valley are here , and you can register here . For details about the other CDNLive events later in the year, see the CDNLive page .![]()
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