UVM, the Universal Verification Methodology, just became IEEE 1800.2-2017. I wondered if that was significant or not, and I knew just the person to ask. Not only that, his office is about ten feet from mine. Cadence had to work long and hard to find someone whose name was Stan to drive our stan-dardization efforts! That's not true, of course, but Stan Krolikoski does have that position. I first met him when he worked for me at Compass when we acquired CLSI, who produced parsers for VHDL and one of the earliest formal verification products that Stan claims to have erased from his memories of that era. He is the only person I know with two PhDs. His first is a "real" one, in that his PhD really is in philosophy. Having discovered that well-paid professional philosopher is not a thing, he did a second one in Computer Science. If you like connections, there is a famous problem in CS known as the dining philosophers problem. Stan joined Cadence just over 10 years ago. I should say re-joined since, like many of us, he had a previous tour of duty. He told me that he came back on the day that the first draft of what would become IEEE 1801 was submitted. That was the universal power format, UPF. Cadence had CPF. It was the most recent "standard war" among EDA companies. Stan, however, was on a mission to eliminate standard wars. The VHDL and Verilog Standard War Probably the biggest standard war in EDA wasn't even between EDA companies, it was between Verilog and VHDL. Verilog was created by Phil Moorby at Gateway, which Cadence acquired. (See my post Phil Moorby and the History of Verilog for more background, including the sheet of paper on which various alternative names were considered.) Verilog was proprietary to Cadence but another company, Chronologic (which was acquired by Viewlogic and then subsequently by Synopsys), created a compiled simulator that was much faster at the time. Eventually, in 1990, Cadence created Open Verilog International, OVI, and gave up control over the language. VHDL had created VHDL International a little earlier, in 1988. The VHDL language was never proprietary, it was developed with funding from the US government (the V in VHDL stands for VHSIC, which in turn stands for very high-speed integrated circuit, a program driven by the Department of Defense). Gordon Bell, who is probably most famous for his time at Digital Equipment but crossed paths with me when he was chairman of the board of Ambit Design Systems, said "the only reason for VHDL was to force Cadence to put Verilog in the public domain." Like many aphorisms, there is more than an element of truth there. Once Verilog was not proprietary, it became the main RTL language, and VHDL remained a niche language used for military projects and, for a whole set of reasons, FPGA design. Ten years later, when Stan was at Cadence for the first time, in 2001, VHDL International and OVI came together to form Accellera, and that standard war was over. The Accellera name came from Gabe Moretti, who insisted it should have an Italian name. If you've ever tried arguing with Alberto Sangiovanni-Vincentelli, you already know that Italians can be very proud about all things Italian. When Simon Davidmann created Co-Design Automation, Phil Moorby got a second go at creating a language. It was called Superlog, but Accellera had a policy of not using a donor’s tradename. In a committee meeting numerous names were suggested—and rejected. Everyone was at the point of exhaustion. “Let’s call it SystemVerilog," Dennis Brophy suggested. "Any objections?". No one had energy for objections, not even the Italians. By that time Co-Design’s contribution was joined by Synopsys' Vera verification language, donated to Accellera in 2002, as well as assertions from Intel, and many borrowed concepts from VHDL, like packages. Everyone had skin in the game. Verilog and SystemVerilog all got merged together into IEEE 1800-2009 (2012 is the latest version, though). UVM on a Napkin Back in 2007, Synopsys had created an influential book, the Verification Methodology Manual , which made them the thought leaders in verification. Stan had just re-joined Cadence and Mike Fister (the then-CEO) pushed for Cadence to be more visible in verification. Stan decided to see if Mentor wanted to work together on a standard methodology. He met with Mentor's Dennis Brophy in PF Chang's in Stanford Shopping Center. They drew up an outline of what became UVM on the traditional napkin (unfortunately, nobody kept it). At the time, Mentor had AVM and Cadence had ERM, which came from the Verisity acquisition. Stan was not greeted with open arms when he returned to the office saying that we should team up with Mentor to create a product that both companies would give away for free. It would be the first time that two EDA companies had worked together like that. Moshe Gavrielov, the pre-acquisition CEO of Verisity, was still at Cadence (before he left to be CEO of Xilinx) and he bought into it. Development began. The two companies created a UVM User Group to help establish the methodology for both companies. But sometimes customers have other ideas. A few major semiconductor companies basically said "You will make it a standard." They rolled Synopsys' register language RAL into the methodology and suddenly all three major EDA companies were cooperating, which was something new. In 2011, it became an Accellera standard and subsequently was submitted to become an IEEE standard. Around then the idea of open source was catching everyone's attention. Often, open standards have reference implementations (SystemC had one, for example), but usually it is correct but too slow for real work. This time there was open source software associated with the standard, available under a standard Apache 2.0 license (nothing to do with the Apache EDA company that ANSYS acquired, this is the Apache web-server used by most websites, which is open source). There are several open source licenses (BSD, GNU, Mozilla, and more) but Accellera standardized on Apache 2.0, and it looks like IEEE may also, although for now IEEE just covers the standard and not the source code of the implementation. No More Standard Wars Since the success of UVM, I think it is fair to say that Stan has got his wish for "no more standards wars." The portable stimulus standard (PSS) is being developed in an open way with a lot of participation from Cadence, Mentor, and Breker. High-level synthesis is all based on SystemVerilog, SystemC, and C/C++, which are all standard anyway. Companies, including Cadence, compete in IP but not in the formats in which it will be delivered. There are probably others I can't think of right now. So, as of April 11, there is now a new 1800.2-2017 - IEEE Approved Draft Standard for Universal Verification Methodology Language Reference Manual . It took ten years but that napkin in PF Chang's became an IEEE standard. Truly a Stan-dard.![]()
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