The 6th RISC-V workshop was held in early May. It was the first one in Asia, at Shanghai Jiao Tong University and was co-sponsored by the University and by NVIDIA. Why NVIDIA? Partly because they have a sizable Shanghai office. But as I wrote last year in RISC-V Gathering Momentum , all future NVIDIA accelerator chips will have a RISC-V control processor as the successor to their home-grown proprietary processor used until now. One of the keynotes, in fact, was on the details of this decision and NVIDIA's involvement with RISC-V (see below). But NVIDIA building a control processor is not what I consider a mainline use of RISC-V, and in any case, it was announced over a year ago. One of the reasons I attended the workshop was not to get the technical details; rather, to get a sense of whether RISC-V is gathering momentum and going to be a significant force. I'll come back to that at the end of this post. In his presentation, Rick O'Connor, executive director of the RISC-V foundation, said that "multiple commercial silicon implementations should be for sale later this year." We will have to wait to find out just what that means in reality. Shanghai Maglev One unique experience you can have in Shanghai is to take the Maglev from the airport into town. It is apparently the fastest commercial train in the world. Its maximum operating speed is 431km/h (268mph) although at times it is slower. When I took it, the top speed we went was 300km/h, which is just under 200mph. For some reason, it only runs at full speed in mid-morning and mid-afternoon. I guess it's the fastest I've been without flying (although technically it is flying since the train doesn't touch the tracks, it has ½“ clearance). RISC-V Introduction The workshop proper was preceded by what was billed as an introduction to RISC-V. The morning consisted of three presentations. The first was by Dave Patterson (who recently retired from Berkeley) on 50 Years of Computer Architecture . It was a fascinating run through the invention of the ISA as a distinct concept, the CISC/RISC wars, the x86 story and more. Since Dave retired last year (although he said he was now working with Google), it was also a sort of career retrospective. I will cover it in its own post. The next presentation was by Krste Asanović about the RISC-V and the motivations for its development. It was roughly a repeat of his presentation at DAC last year, which I covered then: Instruction Sets Want to Be Free . One of the points he always makes in favor of a non-proprietary ISA is that it doesn't necessarily die if the company does. For example, the DEC Vax and Alpha instruction sets (not to mention earlier PDP 11 instructions set) died with DEC. Ownership of instruction sets can also affect this. For example, Sun had put the SPARC instruction into the public domain (it is even an IEEE standard) but Oracle has taken a different view and the latest developments are proprietary. The acquisition of ARM by Softbank hasn't changed anything in the short term. Right on cue, just a couple of weeks ago Imagination announced that the MIPS product line is up for sale. Who buys it (or not) may matter a lot as to what sort of future that ISA has (or doesn't have). The third presentation of the day was Rick O'Connor, executive director of the RISC-V Foundation. He told us that there were now 60 companies signed up and lots going on, but since he gets to see behind the curtains, he cannot talk about everything. As if to show how fast everything is going, Larry Lapidus of Imperas in his short afternoon presentation said that they must be the most recent member to join—just a couple of weeks earlier—only to be outbid for that honor by SecureRF, who had only been a member for about 48 hours. The workshop in Shanghai was the 6th RISC-V workshop. And the 6th workshop to be sold out. He said that it was the fastest standard uptake of anything he'd ever seen or been involved with. "This next year will be exciting as some of this stuff gets rolled out." The Workshop Proper For my summary of the last workshop held in Mountain View last November, see my post RISC-V 5th Workshop Highlights . I won't run through all the presentations for this one. Videos will be available and you can watch an area of particular interest yourself. The program for the three days is here , and if things operate as in the past, this will be updated with presentation slides and videos as they get made available. Here is a summary of the two interesting panel sessions, and some teasers for other parts of the conference that I'll cover in a later post. Panel: RISC-V in China The first day's panel session was on RISC-V in China. Apart from Charlie from Andes returning, I didn't catch everyone's names, but there were two from Chinese academia, a semiconductor provider, a large system supplier in the Chinese market, and someone representing startups. A few especially interesting points came out. One difference from the US is that few people in universities do research in computer architecture. In fact, there are only a few courses. This means that RISC-V cannot start from the universities. It is really hard to hire graduate students since they all want to do "this internet stuff" and nobody wants to do hardware in university. However, unlike in the US, there are a lot of well-funded startups every year. ARM is the default choice, and in China, it is "very cheap" (pirated versions abound). But "free" is not the most important aspect; there must be a solution so that they can build product. Hardware (like RISC-V) is not open source in the same way as software that you can just download and get started (like Hadoop). How many people can even it out successfully? Dave Patterson suggested that the Chinese government, sinking literally billions into the semiconductor industry, should spend some money to train 1M students and get them to build a real chip. Getting a chip is so exciting. But like bureaucracy everywhere, this seemed harder than it should be. Even startup semiconductor companies have difficulty getting funded. "You have to do something first and then try and get grants." The point was re-emphasized that education is a long shot for RISC-V to be successful. It is a long slow buildup; RISC-V needs success now so one key is to make everyone feel it is really easy to move to RISC-V. Run some courses on switching, get companies involved. There are two things RISC-V needs to pay a lot of attention to: Big companies entering the IoT market What the Chinese government wants to happen If you understand those two things, then RISC-V will be very successful. The Chinese government is not driven by purely financial considerations; it wants "made in China" and a culture to compete in the world. In China, RISC-V looks too much like a company and not a technology, so it doesn't feel like Chinese have any ownership of what they do. They feel that RISC-V is "American." Bunnie Huang Keynote The keynote on the second day was by Bunnie Huang, titled Impedance Matching Expectations Between RISC-V and the Open Hardware Community . There is a whole world out there that I didn't know existed, of people who are so passionate about having total control over their hardware that it is almost religious. They will not buy anything that they cannot check themselves. This works fine for software, not too bad for board-level design, but fails totally at the IC level. I think a lot of the proposals are naive, but there is some interesting food for thought in there, so I will cover it in a separate post later. RISC-V AMA (ask me anything) If you are a user of Reddit, then you know what an AMA is—ask me anything. Someone (usually someone famous but sometimes just someone who did something unusual) just answers questions. If you want to get mocked mercilessly, then pretend you are doing your own AMA as a famous person, and then get your publicist to answer the questions. Anyway, the second day's panel was an AMA with the creators of the RISC-V ISA: Krste, Andrew, Yunsup, and Dave. The first question was by Rick and was a complete setup. He asked about verification suites. It turns out that when everyone is asked about the importance of verification suites their hands all go up. When asked who will chair the working group they all go back down. It looks like someone might be stepping up during the workshop. But it is an issue since there needs to be a way to decide if an implementation of the RISC-V ISA correct. They were asked about the RISC-V ISA and Intel. An instruction set and a corporation are not the same things; "Anyone has a better instruction set than Intel, but they are a corporation." Next question was why they are always compared to ARM. "ARM is the only RISC left standing, so it is the obvious thing to compare to." A question about what was the worst weakness of RISC-V got the answer "the software ecosystem." But also that it is changing fast, even in the last 6 months. ARM has 15 years of stuff with people building IP around the ARM, will they do it for RV. Linux had these issues vs. Windows, and the community-built drivers etc., and then companies then started to put people on it full-time. RISC-V has the same opportunity, will people volunteer their time. I asked about what was really going on in industry. It seems RISC-V has won in academia. Is it like Pascal (used for teaching) vs C (used for real work)? I noted that nothing new was announced during the workshop from industry. Google, Oracle, HP etc are all members. The answer was that it does seem that there is stuff going on that nobody can talk about. "Companies don’t talk about what they are doing until they’ve done it." The conversation moved onto Chisel, the hardware design language that was used to define the original Raven chip and is used in SiFive. Dave Patterson got on his soapbox: "You need to move away from Verilog, it’s an embarrassingly ancient technology." "Sorry, Paul," said Krste, "But a whole CAD industry was built on fixing what’s wrong with Verilog. It’s like programming in assembly code. Chisel is just tremendously more productive. We can just write software to do a lot of things without needing special tools." Dave pointed out that "Programming languages have made huge strides in the last 20 years, no longer all Algol-60 derivatives. Hardware designers should leverage that." If you want a little more info on Chisel, see my post A Raven Has Landed: RISC-V and Chisel . Conclusions It was interesting that after the AMA a woman from [redacted, famous big fabless semiconductor company] thanked me for asking the question about whether real stuff was happening in industry or whether all the action was in academia. To me, it is the biggest question about RISC-V. I chatted with her for a bit. She is involved in their processor development and "mostly" works on ARM. I didn't put her on the spot by asking her directly if they are doing any RISC-V development, but I got the impression something is going on. After the 3 days, I'm convinced that RISC-V is going to be dominant in academia, for computer architecture and research in that area. The standard computer architecture books are going to be RISC-V and that means that eventually, all students who know anything about computer architecture will know RISC-V. I've seen this before with Verilog when semiconductor design switched to synthesis. Actually, individuals didn't really switch, the old schematic-based designers moved on and the new kids from school all knew Verilog and synthesis. But that's a long game. However, as was said earlier: "Companies don't announce anything until they have done it." In the AMA, in response to my question, one of the panelists said: "if nothing has happened in a couple of years it will be really bad." Others dropped hints that they knew about stuff that was happening but couldn't say anything. We will see. It looks like there could be some significant announcements in the next year or less. Things can change overnight. If a major cloud datacenter vendor said they had built their own RISC-V server chip, that could change everything on the spot, for example. But the next year will be critical for enough to happen if RISC-V is to achieve its "modest goal": Our modest goal is to become the industry standard for all computing devices. Save the Date The next RISC-V workshop will be held at Western Digital's SanDisk facility in Milpitas on November 28-30th (the week after Thanksgiving, as always). And as always, for all things RISC-V go to the foundation's website .![]()
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