This is the third post on the second Samsung Foundry Day held recently. The first was Samsung Foundry Forum: Roadmaps . The second was Samsung Foundry Forum: EUV . Device Architecture Beyond FinFET In the first post I wrote about the rest of the Samsung FinFET roadmap and even a hint of GAA that is coming next. Obviously, they are doing everything that they can to boost FinFET. As imec's An Steegen said to me once, everyone's roadmap is to get as much as we can out of FinFET before we are forced to do something else. Mark Rodder, SVP of logic technology laid out the view through the front windshield. As always, the careabouts are small cell area, better electrostatics (low leakage), and high drive (performance or low dynamic power). If you don't have those, then the old node will be more attractive than the new. The basic cell architecture is limited by the contacted poly pitch (CPP) and by the Mx metal pitch. To reduce cell height, we can depopulate the fins and go from three fins to two fins per device, and scale the fin pitch. We can reduce cell width by scaling the gate pitch, which means scaling the metal. To improve the electrostatics, we need to go to some sort of gate all around (GAA) technology so that the channel is controlled on all four sides. Horizontal nanowires (NW), where the gates can be stacked, are the most attractive, but each nanowire has a very small Weff, which we can increase in the same area (but not the same cost) by stacking more and more. The alternative of vertical NW cannot be stacked and is unattractive for some other reasons. We can improve with GAA nanosheets (where the wires are spread out into thin sheets, but wide). These can also be stacked. The electrostatics are all better than FinFET but Leff per area is worse. The vertical nanosheet is worse still since there can't be any strain engineering but with horizontal we still have that. Sheets are easier than wires for patterning. As to power, a horizontal nanosheet FET can provide frequency improvement. So of the possible architectures (horizontal nanowire, vertical nanowire, horizontal nanosheet, vetical nanosheet) it ssems that horizontal nanoesheet is the clear winner. In fact since the foundry day, Samsung (along with GF and IBM) announced that they have developed such a process for 5nm (see the above photomicrograph). Some other points Mark made: He showed horizontal nanosheet GAA hNS FET (also called MBCFET to make it more confusing) layout No need for dummy stacks like dummy fins Single stack of wide naonsheets for nFET and pFET combined with contact over active achieve sufficient Weff/cell-area to extend architecture for multiple nodes (after 5nm!) That's a lot of detail. The takeaway: GAA horizontal nanosheet FET is the key direction for architecture beyond FinFET FD-SOI Samsung has two process families. FinFET and FD-SOI. Yongjoo Jeon, director of technical marketing for Samsung foundry filled in some of the details. Samsung licensed the FD-SOI technology from ST years ago at 28nm and that process is mature. The next node is 18 FD-SOI. The FD-SOI structure (on an insulator) is naturally good for RF noise prevention. 28FDS had a fast yield ramp-up. Excellent product yield (d0<0.2). Rapid ramp up to mass production. There is a broad IP portfolio and reference flows from companies like Cadence. At the recent SOI Symposium, NXP announced the first FD-SOI product based on 28FDS, some of their i.MX microcontroller line. It is lower power than previous version. Lowest SER capability for automotive. Utilized full range of back biasing. 18FDS is a cost reduction and lower power and same BEOL as 14nm FinFET. It has RF/eMRAM support. The smallest standard cell height (576nm). Target PPA vs 28FDS is performance up 20%, power down 40% and logic area down 30%. Power comes from voltage reduction, plus area scaling contributes. RF Next, he moved on to RF-SOI. Mass production PDK available. Two metal stack options. PDK improvement 67GHz but will have 110GHz by end of June. Higher fT than 28 bulk. Lower power, lower vt with body biads, high intrinsic gain. 1/f noise of FD-SOI is lower than bulk. New mm-wave PCell support. Physical isolation structure of SOI means “no guard ring” giving area benefit. eMRAM Memory can be capacitance based (flash) or resistance based. But as this scales, the number of electrons on the capacitor gets less and less, meaning that 28nm may be the last eFlash node just because of that. eFlash isn't that friendly with new materials (HGMG, gate-last etc) anyway. So for all these reasons, the future is eMRAM. 28nm MRAM to be embedded in Cu BEOL (MRAM is built in the interconnect, so doesn't depend at all on the FEOL) with only three additional mask layers. It has superior write speed and endurance compared to eFlash. About 1000X faster to write than eFlash. eMRAM roadmap: Demonstrated on 28LPP. First prototype of 28FDS+eMRAM taped out early 2018. It will be qualified by end of 2018. No dependence on FEOL makes for easy migration to advanced nodes. Will be at 18FDS and even 14nm FinFET. 4th Industrial Revolution Yongjoo wrapped up saying that these are three brilliant soccer players: FD-SOI, MRAM and RF. But like a great soccer team, they are even better combined. Guess what an IoT device usually has on it? Integrated IP in a single chips for data processing, memory, and connectivity, so requires all three technology (RF, memory, processing). So the partially executed game plan is: Million wafer seller 28LPP, with eFlash and RF to get the ball rolling—DONE Next, FD-SOI—DONE Then move from 28nm to 18nm—ONGOING Finally add eMRAM as the future of eNVM—COMING Conclusion Combining FD-SOI/RE/eMRAM will be one of the futures, the other being GAA horizontal nanosheet FETs.![]()
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