On Tuesday, Cadence hosted a lunch focused on 7nm digital design and signoff. Jim Hogan was the moderator. The panel got to debate 7nm while everyone else got to eat lunch. For more details on 7nm, seem my post TSMC @ N7 with Cadence . In particular, there are explanations there of cut masks, via pillars, and non-Gaussian timing, which got mentioned in the lunch panel. EUV (extreme ultraviolet) also got mentioned. If you need background, try my post EUV Might Really Happen . Each member of the panel started of with a brief position statement. They were: Rob Christy of ARM. Rob said that ARM has been working with 7nm for about a year, building large interconnect devices with multiple CPUs in the enterprise network space, and it is attractive for density, power, etc. Other parts of ARM are also pushing to 7nm, including mobile. Anand Rajogoplan of Mediatek. Anand said that mobile continues to grow and continues to be exciting. In 2017, 50% of all mobile traffic goes through mobile phones, 10 years ago was 1%. And it has grown a lot, too. Was single core, now multiple core, 2+GHz. Key to fuel growth in mobile, especially mobile gaming (biggest sector in gaming). 7nm is the foundation for the best end-user experience including dual cameras, efficient connectivity, and high bandwidth. Kazuhiro Takahashi of Renasas. Kaz said that Renasas is a solution provider in automotive, home, etc., and so advanced technology like 7nm is a key technology to provide better solutions. Tom Quan of TSMC. Tom said that you can hear from Mediatek and Renasas that smart mobile has been the driver, and now automotive is a big driver. HPC, too, especially in terms of wafer revenue. TSMC have been working with 7nm for two years. In risk production already. Customers doing tapeouts, next year will be full-volume production. Lots of adoption from about 30 customers at 7nm. Smart mobile has a lot more processing now, some AI starting to get built in. In HPC, all those racks to process the data from all the devices. ADAS/automotive requires local processing so also pushing to 7nm. Mitch Lowe of Cadence. Mitch said we, Cadence, are seeing high demand from many customers: networking, datacenter, high-end mobile, automotive. Everyone is moving aggressively to 7nm. We have now been certified across many test chips. Full flow is now faster and smarter than ever before, injecting some machine learning into it, too. High-speed IP for high-speed datacenter, memory, and more. So we are part of this 7nm revolution. Aperitif: Benefits of Moving to 7nm? Anand: We need more features and more processing power. This is enabled by new nodes like 7nm. Kaz: Yes, we need performance at low power, especially to process automotive vision data, so we need 7nm to do it. Tom: Compared with 16FF+, 7nm is about about 35-40% faster and 60% lower power. In terms of density (routed gates), it is 3.3X more dense, which is amazing in just a couple of process generations. SRAM is 0.37 times the size. This is a major improvement. From a schedule perspective, we've been working with Cadence and have all the flow certified in March. We have 17 or 18 tapeouts expected this year. About 15 going to early production, but real volume production is next year. Starter: Tools and Flows Tom: At low voltage, there is more variation, more challenge in terms of timing. Different innovation for OCV (on-chip variation), parametric OCV, statistical OCV. Not to underestimate the collaboration for a year and a half for things like cut metal. In the past, we just had minimum spacing, but we wanted it much closer so have separate metal cut mask. P&R and the tool chain has to deal with this, starting a couple of years ago (early in the cycle) so there was time to get it all developed. Kaz: Even for automotive, with big batteries, it is all about saving power. For 7nm, the wire resistance is larger and the wire delay is thus longer, which makes timing optimization more difficult. Anand: We used to worry about stuff like DRC late, but you can't do that any more. We need the power grid to be perfect and optimized up front so that you don’t lose the advantage of new nodes and comprehending these new priorities. Rob: Yes, it just has to work. We’ve all alluded to the fact that you have to plan much more than ever before. Basic P&R flow has to work, there is no hand fixing, hand polishing. 2000 violations, crank through and fix. Now design rules are too complex and you can’t fix it up no matter how big a team. The tools have to be perfect. Anand: Yes, it is important for the tools to be DRC and timing-ready up front. Wires are really important and optimizing the wires is going to affect the power. But the design has to come out clean, we have very little room to do anything after the fact. That is key to realize the value of 7nm. Tom: We were working together with Cadence really early. I already mentioned a couple of basic challenges: cut metal, resistance. Now in routing, we know lower layers are higher resistance and we minimize routing on lower layers. But when promoted to higher layers we connect through via. Regular via won’t work. Stacked via won’t work. So we created a pillar with parallel structure in middle layer. But understanding how to use that has to be comprehended by the tool and the libraries. But the decisions end up being made earlier, at the synthesis stage. So for the first time, TSMC/Cadence had to bring synthesis into the cycle. We have worked together very closely. The optimization tools have a better picture of the whole design and how to optimize it. Mitch: Machine learning is a big deal. We continue to work with TSMC to fix things at DRC level, but need really good prediction and analysis. Humans can’t really do more than look at the color map, but need predictability of congestion up front. Synthesis through final signoff, we use same engines throughout that has really helped. Layer promotion, moving the routing to higher less resistive metal is important but so is automatic selection of wide wires and spacing. However, this has to be automated, you can’t do it manually. Getting the new via pillars right for the clock has been a challenge. We have learning still to do, but everything is a lot better than in the beginning. Entrée: How Is IP coming? Rob: What we learned at 16nm didn't translate that well to 7nm, to be honest. It is a big challenge. DRC, especially, is a huge challenge since it is all but impossible to fix anything by hand. The big challenge is to keep the high-end performance while delivering the density and power. The power grid is another particular challenge. The via pillar is not optional. You need it on the clock network. As an IP supplier, we know what microarchitecture changes we need based on implementation. Some IP doesn’t necessarily scale. Wiring is a huge problem, especially on lower level metal. Vias are not scaling how we would like. From IP point of view, we need to be able to prototype and capture the gotchas, but the back end is creeping in and DRC is part of the optimization space. AI is the only way to do it, looking at dynamic IR drop or thermal, then you can’t do it. Mitch: Cadence has been working as the process evolved and even during the period when the EDA tools were still being developed. At 7nm, a lot of what used to be analog IP is now mixed signal with a large digital component. Mixed signal used to lag a bit behind pure analog and pure digital, but now with these IP requirements it has to be right up there at the same time. Another challenge, more for the tools, is that cells at the lower level are tiny, and so accessing the cells and getting the power grids correct is really critical. Kaz: Even IP suppliers like ARM now need to worry about EM effects and have them fixed before we get the IP. Tom: Early test chips include test structures from IP vendors. Foundation IP obviously has to come first. But interface IP is already on the test chips. We should see results from test chips and production tapeouts later in the year. Dessert: Is Doing a 7nm Design Suicide? Tom: It is one thing for, say, Qualcomm with endless resources. How about a small fabless company? But the same question was asked about about FinFET and now it is everywhere. We believe 7nm will be a long-lasting node with a very, very fast ramp. Mobile computing continues to need it, HPC has even higher demands, then automotive level 4/5 needs a lot of compute power in the car, so 7nm will be everywhere. Kaz: Introduce EUV as soon as possible! Tom: We are introducing N7+, which replaces multiple masks with EUV. So, one year from N7, we will have EUV. Anand: We rely on EDA and foundry partners. As Mitch mentioned, it is important to be able to have tools that are optimized to provide the best PPA so we can realize the benefits of 7nm on the first design. Rob: Design is often going to dictate the node. A lot of rapid development as the tool and EDA space matures and it will happen. 2017 is not the year for 7nm as a mature node, but the problems we have seen will get resolved in 2018. Can we do it now? Yes, but there are still a few issues. We would still like to further improve performance. You are not going to lose your job doing a 7nm design! Mitch: Not at all. It's tough, but doable.![]()
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