The Wednesday of DAC means the Cadence Mixed-Signal Lunch. For the Digital Lunch, see my post Table for 7—Lunch at the Leading Edge . The mixed-signal topic was Overcoming Mixed-Signal Design and Verification Challenges in Automotive and IoT Systems, although with Bosch and ST on the panel, there was definitely more emphasis on automotive, as there seems to be everywhere in semiconductor these days. The moderator was Professor Sayeef Salahuddin of UC Berkeley. The panelists were: Pierluigi Daglio of STMicroelectronics Suresh Jayaraman of Amkor Goeran Jerke of Bosch Vinod Kariat of Cadence Introductions The format was that each panelist made a short presentation on their position. Then the discussion was immediately thrown open to the audience to question the panel. Pierluigi of ST opened the show talking about BCD. This was invented at the end of the 1960s at ST and the next generation is down to 90nm. At that node, they can go to 2M transistors. The big thing about BCD is being able to control high voltages, up to 40V for ABS, 100V for fuel injection, and 800V for electric traction ("or even more," Pierluigi casually said). The process is beyond mixed signal, allowing not just analog and digital, but also power and ePCM (embedded phase change memory) on the same die. Pierluigi had a shopping list of wants: Faster transistor-level simulation More intelligent and adaptive AMS converters Reliable in-design tools for early bug prevention Specification and data sheet management Effective post-layout signoff analysis Next up was Suresh from Amkor, who talked about advanced packaging technology (since Amkor is the #1 OSAT running at around $1B/quarter). He said that the industry segments driving packaging technology are mobility, IoT, automotive, and HPC. In particular, system-in-package (SiP) is in all four markets, with more and more functionality being integrated at the package level as opposed to the chip level. The big trend is to fan-out wafer-level packaging (FOWLP). Goeran went next, and opened with some statistics about Bosch. You probably already knew they are a top automotive supplier. You probably don't know that they have 276 manufacturing sites and 380,000 employees (of which around 60K are in R&D). They are about $80B in annual revenue. But they are not just in automotive, almost every mobile phone contains at least one sensor from Bosch. Automotive is clearly a big trend in semiconductor, but the next level down the big trends in automotive itself are: ADAS and autonomous driving Power train electrification Connectivity (V2X) It used to be that automotive was many process generations behind the leading edge of Moore's Law, which Goeran called automotive's "comfort zone", using processes that already have 5-10 years of maturity and reliability data. That is no longer the case and, apart from the challenge of designing on advanced processes, the reliability issues add a big uncertainty. The level of integration causes organizational challenges, too, since it is no longer possible to develop product for each segment in separate independent groups, often multiple technologies are integrated on the same die or in the same package. Finally, Cadence's Vinod talked about trends in the tool area for automotive and IoT. The big areas of interest and concern are: Mixed signal Verification PPA Validation Time to market IP integration One big ongoing change is that IP/chip/package/board all used to be separate spaces with separate specs. But now people want to analyze the chip in the context of the package and board, not just for electrical but also thermal. Questions Question: All these requirements for quality and reliability mean that we have to launch an intensive number of testbenches. Does ST or Bosch have any times on how to balance the number of jobs with effective license management? ST: There is need for regressions suites for AMS since spec needs to be checked. The foundation is obviously the speed of the simulator (Spectre). Monte Carlo requires a lot of simulations. We are trying to apply digital techniques to analog. We are trying Cadence Virtuoso ADE Verifier starting from Excel and mapping to simulations, then run in a single shot all the simulations. There is an assistant to take the data and make comparison to generate a report automatically. As to the license part, we have some techniques in our farm with different queues depending on length of job, amount of memory, etc. Bosch: We also use similar approaches. We spend a lot of effort and money on bringing the requirements into the engineering world. Unfortunately there are more gaps than we want. It is an opportunity for EDA. Run times are sometimes in weeks, which is very painful. We can’t run full chip simulation for robustness analysis. Of course we use high-level system modeling to bridge the gaps. There are also some issues where simulator technology could improve, we are working with Cadence on those. Scaling of simulation is becoming an issue. You need 100s of licenses and a big farm to run the regressions. Terabytes of data needs to be analyzed. Capabilities have improved a lot but there is still more required. Reliability and robustness is not feasible at the chip level. We try to break everything and see where the critical failure mechanisms are. Even that takes several thousand hours. We also see some needs for electrical rule checks since we can’t always simulate everything. We have lots of knowledge developed over the years but we don’t assume we can simulate every effect. We still need to use the real world: “Test drives in Sahara, Sweden…Indonesia is quite nice.” Cadence: I would have said some of these things about tools for verification and regression management. We have a continuous effort to parallelize more. We are focusing on specific things for reliability. There is a lot more EM/IR analysis than five years ago. Aging and fault modeling are new areas since reliability is becoming more important, and can’t just do with functional verification. More challenging in analog world than digital since the methodologies are not set up for that. It is hard to even know what the “worst case” is. Another comment, we see in future more and more usage of the cloud. Everyone is dipping their feet in the cloud (mixed metaphor, I know). This is driven by what is needed for peak demand and time-to-market pressures. Amazon and Microsoft have substantial farms but there remain some technical, legal, and business challenges. Q: Regarding integration of analog and digital in automotive for autonomous driving, does Cadence offer some features to integrate within system-wide engineering systems such as DOORS [a requirements tool from IBM/Rational]? Cadence: We do some things in our verification cockpits for passing data back and forth. But not today with system-level requirements, system-level management systems. Q: Dynamic simulation and co-simulation will be time consuming and slow, FMEA and FuSa simulation even worse. From the automotive industry side, given these bottlenecks, what do you practically expect and what flows? Cadence: Let me paraphrase. Circuit simulation is time consuming. The thesis is that it is infeasible, not sure I agree. How do you look at things like fault analysis and how to apply to analog world? For fault simulation and analysis and extending to FuSa, this is a big area of discussion. There are partial solutions, but I won’t talk about stuff we don’t have yet. But there will be solutions extending FuSa approaches into the analog space, I expect that to happen. Circuit checks are another static approach. EM/IR is pseudo-static approach. We will see more and more specialized static analyses complementing dynamic simulation approaches. Analog has so many degrees of freedom that you can’t expect the same level of automation and analysis as in the digital world. It is still a mixture of art and science in analog world. You are not going to push a button and get told the design is clean. Bosch: Analog fault simulation is an area of active research. What is done today is a lot of things we do as a precaution so that we can test critical systems at transistor level, which makes designs more complex and costly. For example, if you have an airbag system, you want a clear signal if the airbag should go off or not. ST: Static checks are the future. It is a speed problem. As many static checks as you can do, clean up as many bugs as possible using electrical rule check, etc. Analog fault injection at block level or system level. At the block level, it sort of works but it is a problem of speed. If you inject one or two problems, you can do it, but if you have to do hundreds and hundreds, it is not feasible today. For sure, it is a hot topic for the future and we are just at the beginning of it. Q: How does packaging come into the picture? Amkor: Signals move into the outside world through the PCB, so there is a signal chain there where the package comes in, and we have to worry how the signals get degraded. The package is part of the chain of reliability in end use. Q: Is package selection done earlier? Amkor: Yes, it is being done earlier. You used to make a die, and then find a package to put it in. But now system requirements are more stringent so it needs to happen at the architecture level, not even as late as floorplanning. The package affects the chip design. Bosch: I see a tools need to pick up failure mechanisms early. Analyze mechanical stress and see which choices are bad and which are not. We need a model for failure mechanisms, it is a top-tier problem. Q: What about mixed-chip integration? Different chiplets made by different manufacturers in the same SiP. Amkor: It is happening now. People don’t want to put everything in the most advanced node for both cost and performance reasons. Can mix and match instead of providing one big SoC that does everything. Cadence: Package/board area is an area we see a lot with serial links and interconnect, etc. It is already a big area, especially signal integrity. Are you getting good eye diagrams? Automotive Ethernet going faster and faster and more effects need to be modeled and signals need to maintain their integrity. ST: We also see need to simulate chip/package/board together. However, not all the tools understand all the package descriptions. We get into trouble when different teams give us it in different formats. Cadence: Another problem is that package, board, and chip people give different names to the same things. We could have a panel just discussing that! Q: Reliability is an order of magnitude worse than conventional electronics that we are used to in automotive. How do people have to go about it in the future? Bosch: If I look five to ten years ahead, we have to trust the EDA tools. We will trust our lives to these autonomous cars in the future. How do we make sure the simulation is right? Some classic techniques like redundancy and self-checking. Resilience is important: an error occurred, how to get back to a safe state. Cadence: All these systems have inherent limits on what their testability is. We continue to work on simulators. There can be bugs in tools, bugs in the models. With core circuit simulation tools, it is very rare that what we get the simulator giving completely wrong results. The challenge is heavy dependency on a designer anticipating the result and making sure that they don’t miss patterns indicating a problem. The biggest challenge is the huge amount of data. Bosch: With autonomous driving, the requirements for whole tool chain will definitely increase. Today we need to make sure all tools are compliant. If the tool makes a mistake, how does it get detected later on? Regarding autonomous driving, this will be come more of a requirement. Q: I've rarely seen people talking about FIT or a die FIT. A lot of data for component level, but it fails to percolate to the top. Is it a gap not knowing the actual failure rate and what it will be at end of life? Bosch: What we have to do is to make sure all applications that we deliver have no failure, they always work. If one or two failures on production line ("a zero kilometer problem") then it is a production stop and a task force is created (this is very unpleasant). Then later on we take all the probabilities and do analysis at the system level during the flat part of the bathtub curve. ST: Same story with us. We do EM/IR analysis. This was optional before, but we have had some recent failures, and now the flows are mandated. One of the areas with the most growth in tool usage for us. And with that, the time was up, and off for a post-prandial coffee.![]()
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