Yes, it's true. After who knows how many years, EDPS is not going to be in Monterey, but in Milpitas. They still seem to be keeping the dolphin logo though. So, yes, dolphins in Milpitas. EDPS is the Electronic Design Process Symposium. It is a relatively small meeting which means that there is lots of discussion. This year it will take place on September 21st-22nd at SEMI in Milpitas, at 673 South Milpitas Boulevard (if you thought SEMI was on Zanker, well, they were, but they just moved). It finishes at 2pm on Friday. This is the 24th EDPS. This year the theme is Efficient Design and Manufacturing . The Keynotes Let's start with a brief tour of the keynotes that are sprinkled through the whole symposium. There are four keynotes over the two days. The symposium opens with a keynote from Antun Domic, Synopsys' CTO, on Exploit the Close Relationship of Design and Manufacturing to Accelerate Product Introduction . After lunch that day, Zoe Conroy of Cisco will talk about Using System Level Testing as a Conduit to High Volume Manufacturing . During dinner, Jim Hogan will talk about EDA Industry's Participation in the Cognitive Age: the Fourth Industrial Revolution . The second day opens with Pankaj Mehra of Western Digital, on Getting EDA Ready for the Data-Centric Architecture . OK, the detailed schedule for the two days is below. On Thursday there are sessions on Design Acceleration, Driving to Higher Yield and Accelerating Debug and Validation. On Friday there is a session on Machine Learning and then a panel on EDA and IC Design, Manufacturing, and Test . The symposium will wrap up mid-afternoon on Friday. The full details are below. Schedule Thursday September 21st Breakfast, registration and all that stuff starts at 8am. The main sessions start at 9am with a welcome from this years Chair, Shishpal Rawat. The opening keynote speaker is Antun Domic, CTO of Synopsys: Exploit Close Relationship of Design and Manufacturing to Accelerate Product Introduction . The morning is then taken up with a session on Design Acceleration, chaired by Naresh Sehgal: Rajesh Gupta of UC San Diego on Compositional Synthesis for High-Level Design John Lee of ANSYS on Big Data and Machine Learning for Chip Design CP Hung of ASE Taiwan on System-in-Package Technology Direction and Design Challenges Bill Bottoms of 3rd Millennium Test on System-Level Design and Simulation for Heterogeneous Integration Then there will be lunch (provided, there is such a thing as a free lunch, at least at EDPS). The afternoon starts with another keynote to wake us all up, from Zoe Conroy of Cisco on Test and Manufacturing Improvements for Product Time-to-Market The first afternoon session is on Driving for Higher Yield, chaired by Herb Reiter and Ron Leckkie: Keth Arnold of PDF Solutions on Expanding Die-Yield Analysis to Include IC Package Impact Asem Salim of Open-Silicon on The Importance of Ecosystem, Especially System-Level Test Gerard John of Amkor on Multi-Die Production Test Challenges Juan Rey of Mentor on Manufacturing Considerations in IC Design Especially for Test The second afternoon session is on Accelerating Debug and Validation at Quality, chaired by John Swan and Priyadarsan Patra: Gajindar Panasar of UltraSOC on System-Wide Visibility in Post-Silicon to Drive Meaningful Analytics Eduardo Bolanos on Validation Analytics: Data You Need at the Speed You Need It Al Czamara of Test Evolution on Integrating Pre-Silicon and Post-Silicon Coverage to Accelerate SoC Validation Vikas Kumar of Intel on Security vs Debug: Challenges vs Opportunities That evening there will be a dinner at Embassy Suites nearby. When you register for EDPS you will be asked to choose between vegetarian, salmon or steak. There is a keynote during the dinner from Jim Hogan of Vista Ventures on EDA Industry's Participation in the Cognitive Age: the Fourth Industrial Revolution . Schedule Friday September 22nd Breakfast starts at 8am. The main sessions start at 9am with a keynote from Pankaj Mehra of Western Digital on Getting EDA Ready for the Data-Centric Architecture . The morning is then taken up with a session on Machine Learning, chaired by Aparna Day: Paul Franzen of NCSU on Machine Learning for Next-Generation EDA David White of Cadence on Machine Learning Approaches for Solving Critical Challenges in Analog Design Rob Aitken of ARM on Machine Learning in ARM Processor Design Jeff Dyck of Solido Design Automation on Machine Learning for Engineering Abhijit Chatterjee of Georgia Tech on Machine Learning in Post-Silicon Validation of Mixed-Signal, Analog, and RF Circuits That will be followed by lunch. After lunch is a panel discussion moderated by Ron Leckie on EDA and IC Design, Manufacturing AND Test . The panelists are: Javi DeLa Cruz of Ivensas Dan Leung of Open-Silicon Keith Arnold of PDF Solutions Derek Floyd of Advantest Zoe Conroy of Cisco There will be a brief wrap-up after that, and at 2pm we can all go and immediately get stuck in Silicon Valley Friday afternoon traffic. Details and Registration Full details, including a link for registration, are on the EDPS Website . Early registration ends August 31st. I'll see you there. Sign up for the weekly Breakfast Bytes email:![]()
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