A couple of weeks ago, I talked to Naveed Sherwani, the new CEO of SiFive. For more background on them, see my post SiFive: a RISC-V Fabless Semiconductor Company . Background Naveed did his PhD in the mid-80s on EDA in general and routing in particular. Then he literally wrote the book on physical design, Algorithms for VLSI Physical Design Automation , the third edition of which came out in 1999. After being a professor and producing 100-odd papers on physical design, in 1993 he joined Intel to work on automating their microprocessor design flow from high-level spec all the way through to high-volume manufacturing. He then joined Intel Microelectronics Services, a subsidiary of Intel focused on ASIC design. That morphed into Open SIlicon where he was involved with dozens of ASICs. He has spent the last three years running a software company and has a good perspective on the difference between hardware and software. Lip-Bu, Cadence's CEO, is a good friend of Naveed's and in fact was a reference for him during the hiring process at SiFive. Walden International, where Lip-Bu is Chairman, is one of the few venture capital firms that invests in hardware and fabless semiconductor startups, and he subsequently called Naveed to encourage him to take the job and to be a catalyst for change. SiFive Naveed told me that his enthusiasm about SiFive is on several levels. First, he has been a student of computer architecture since the 1970s, working with ISAs like the Vax, Intel, and Arm. In fact, during his ASIC phase he worked on hundreds of Arm-based designs. RISC-V is a fresh clean architecture and is bringing new energy to the industry with a working group including the best of the best in areas like memory architecture. The hardware textbooks are being changed and so there will be hundreds of thousands of students graduating over the world already knowing this architecture. SiFive has all the inventors of the RISC-V ISA in one place, and as a result they have people applying to join them, which makes recruiting easier than normal. In addition, there is momentum at the country level in India and China (India has made RISC-V the national computer architecture). Changing the Culture Naveed sees part of his job is to change the culture of the semiconductor industry. As he put it: Do we want to leave behind an industry like the railways, still important but mature, or leave a vibrant, innovative ecosystem? He sees the challenge to make hardware companies more like software companies, where you can get a company to a minimum viable product (MVP) with very low capital, and only then, if it is successful, go and raise the money. SiFive has two inter-related businesses. The first is to supply soft and hard RISC-V cores to customers who are capable of designing a chip themselves. But they are making the IP licensing process very low friction and open compared to what it has been historically. There are no long negotiations where everybody ends up paying a different price. The current contract is seven pages long: click, docusign, done. Pricing is openly on the web, too, and so everyone pays the same price. He realizes they will need a model for startups, too, where up-front money is not required, and so they only get paid once the company is funded and goes to production. For people who don't have the capabilities to do their own design, they have an ASIC business. They keep the costs down by offering very limited options: only a few processes, only a few packages, RISC-V only. For a design at 180nm, they charge $100K and offer a turnaround time of the fab cycle time plus 30 days (that is, they do most of the design part in 30 days and the rest is the time for the foundry to deliver a prototype). Since Naveed has taped out over 300 chips in his career, and done a lot of innovation in physical design and verification, he should be confident of what he is doing. Part of the way he feels that they can do this is that SiFive claims that their RISC-V core has 2X power advantage and 11X performance advantage over equivalent Arm designs. This means that they can afford to do quick and dirty designs and leave some performance on the table for cycle time, and end up with perhaps a 7X performance advantage. By limiting choices and pre-verifying IP, they can have a very fast physical design and verification cycle. He also wants to move to a "no support" model like software companies. Software companies, especially open source, don't help their customers. Customers help each other, with chat rooms, meetups, and so on. That is how they can deliver free versions of their software. He pointed out that Cadence could deliver some of these small startup companies software that is free but with no support. These companies have time but not money. Then the company would pay when they were ready for production. That way the up-front costs of getting a fabless semiconductor company off the ground are not a barrier to it ever happening. As Naveed put it: If 10,000 downloads and only 10% are successful, that is still 1,000 companies for the existing ecosystem to make money from. I remain a bit skeptical that this can be done. The industry is littered with the carcases of companies who assumed that they could dramatically lower the costs of doing design and make good money on relatively low-volume designs. Every FPGA company had, and then gave up, on taking designs that were already essentially done and hardening them. Semiconductor manufacturing is a mass-production process. This means that designs that are not intrinsically high volume have needed to be aggregated. The only really successful way of doing that aggregation has been the FPGA, where the generic silicon runs in high volume and the user customizes it themselves. Even if Naveed is successful at persuading the EDA and IP suppliers to forgo up-front money, there is still non-trivial manufacturing costs for prototypes and significant investment for volume manufacturing. Hardware is simply not software, which can truly be delivered, once written, without any significant cost. Sign up for Sunday Brunch, the weekly Breakfast Bytes email.![]()
↧