One of the highlights at CDNLive India 2017 that was held in September was the launch of the new memory characterization solution from Cadence called the Legato Memory Solution. I had a chance to speak to Dr. Vinod Kariat, Corporate VP of R&D at Cadence, about this new product. Excerpts from our discussion: Vinod, can you please briefly introduce yourself? I did my undergraduate studies at NIIT, Tiruchirapalli and went to the US for my graduate studies. I joined Cadence through CadMos Design Technology, where I was one of the founders. Since then, I have worked in four or five different roles at Cadence. Currently, I am responsible for the development of our custom electrical analysis products. You launched a new memory solution at CDNLive India in September. Can you tell us a bit about that? There are many memory designs being done at advanced nodes in India. So it was a great fit to launch the Legato Memory Solution at CDNLive India. We introduced the concept during my keynote. Then, Invecas presented a paper on their experience using Legato Memory Solution, where they talked about the exponential saving in runtime and run memory that they experienced compared to other available methods. Why are you launching a memory solution? In today’s SOC designs, the memory arrays take up a lot of real estate, and are often in the critical path – for timing, for yield, and often schedule. Memory performance and power requirements are becoming more stringent from generation to generation; so, design and verification engineers are faced with many challenges. Why the name “Legato”? Legato, like Cadence, is a musical term. It means “in a smooth, flowing manner, without breaks between notes”. It is a perfect illustration of our memory solution. We are providing a one-stop shop by integrating seamless our memory design, verification and characterization capabilities. This enables our customers can focus on your design rather than tools or flows. Legato is our solution platform name, we are working on other solutions that will be introduced next year. Stay tuned. What are some big challenges facing memory engineers today? The biggest challenge is time to market – the designs need to be completed, and ramp to yield, in a very short time frame. In this process, memory designers often face multiple tool and flow challenges. One of those flow challenges is that different tools are used for design, verification and model creation steps. Also, when you use multiple tools, you need to ensure consistency. For example, the FastSpice tool used to do margin analysis needs to be consistent with the tools or scripts used to generate Liberty timing and power models. With our Legato memory solution, our customers can focus on delivering their memory on schedule, with the right performance and power, rather than on tools or flows. Can you provide an overview of your memory solution? We are providing a single solution for all memory design, verification and characterization needs. Typically, there are three separate use cases: bit cell design and variation analysis, full memory instance analysis and verification, and timing and power characterization. In Legato Memory Solution, we provide cockpits to cover all of these use cases, with guaranteed consistency between the different use cases. Who are your target customers? Our memory solution targets memory IP vendors, such as foundry memory and memory compiler teams. It can also be used by SOC design teams building custom memories. And stand-alone memory chip vendors are our target customers too. We introduce Cadence memory solution with SRAM support, and will follow up with DRAM and other types of memory support. Excited to know more? Click here . Also, Paul McLellan's Breakfast Bytes covered Legato: Smooth Memory Design .![]()
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