Every December is IEDM, the IEEE International Electron Devices Meeting (IEDM). This year it is the 63rd, which partially explains the odd name. When it started, an "electron device" was a vacuum tube (we call them valves in England) and only a couple of papers were about those new-fangled transistor thingies. This year (and probably forever) it will take place in San Francisco at the Hilton Hotel on O'Farrell Street, from December 2-6th. I will be there, and so you can expect several posts about it here on Breakfast Bytes in December and January. If you want to know what is coming in the process area, then this is the best place to get an in-depth look. The things that get discussed here eventually find their way into design tools and design methodologies, so they affect everyone in the semiconductor ecosystem. On the other hand, you have to know enough about process to be able to understand the presentations (and some, unless you have a Ph.D. in the area, will be incomprehensible). Remember, "you can only learn something if you almost know it already." The conference will take the same format as usual, with educational events on Saturday and Sunday, the conference proper Monday to Wednesday. Saturday: tutorials on topics like silicon photonics and negative capacitance transistors Sunday: short courses, always one on logic and one on memory. This year the logic one is Boosting Performance, Ensuring Reliability, Managing Variation in sub-5nm CMOS and the memory one is Memories for the Future: Devices, Technologies, and Architecture. They run in parallel but with a press pass I get tickets to both so I will try and at least partially cover both. Monday: plenary sessions (what other people call keynotes). Multi-Chip Technologies to Unleash Computing Performance Gains over the Next Decade by Lisa Su of AMD Energy efficient computing and sensing in the Zettabyte era: from silicon to the cloud by Adrian Ionescu of EPFL System Scaling Innovation for Intelligent Ubiquitous Computing by Jack Sun of TSMC Development of Sustainable Smart Society based on Transformative Electronics by 2014 physics Nobel prize winner Hiroshi Amano of Nagoya University [this one is on Wednesday, not in the Monday plenary session] After that, the world explodes into 8 parallel tracks through Wednesday. Hidden away in the program are four special focus sessions with invited papers on timely topics. This year these are: 3D Integration and Packaging Modeling Challenges for Neuromorphic Computing Nanosensors for Disease Diagnostics Silicon Photonics. The full calendar has not yet been published, but several especially interesting papers that I've been told about are: Intel and Globalfoundries will each unveil their forthcoming state-of-the-art integrated FinFET technology platforms. (Session 29); teaser picture above, from GF's paper on 7nm Macronix will discuss an ultra-high-density 3D NAND technology (Paper 19.1) IBM’s Dan Edelstein will give a retrospective on copper interconnect and discuss its prospects (Paper 14.1) The first functional circuit built with stacked silicon nanowire transistors, from Imec and Applied Materials (Paper 37.4); teaser picture below, from this paper A 14nm ferroelectric FinFET technology from Globalfoundries, for high-performance, low-power applications (Paper 15.1) A sweat-sensor-based “Laboratory on the Skin” from Switzerland’s EPFL (Paper 18.1) Four novel implantable microfluidic devices for a variety of diseases/chronic conditions, from Houston Methodist Research Institute and Italy’s Politecnico di Torino (Paper 10.1) A poster session on MRAM memory, an emerging non-volatile memory technology that is attractive because of its size, speed and low-power requirements, and which is in the process of commercialization; the poster session is sponsored by the IEEE Magnetics Society Copper Interconnect As I mentioned above, IBM's Dan Edelstein will give a retrospective on copper interconnect. Before copper, interconnect was either aluminum (or aluminium as they say in the UK, as they did in the US up until about 1900) or a titanium-tungsten sandwich, written TiW and pronounced "tie-tungsten." Here's your trivia fact of the day. W is the chemical symbol for Tungsten since it is also called Wolfram because it was first isolated from the mineral wolframite by a team in Spain. But earlier a team in Sweden isolated it (or at least a compound containing it) from a different mineral, tungsten (which apparently means heavy stone in Swedish). In English, it is normally called Tungsten but the symbol is W. Aluminum and TiW interconnect were created by sputtering the metal(s) onto the wafer, and then using plasma etching to remove the unwanted metal between the wires. I don't understand the details of why, but copper cannot be plasma-etched. It had long been thought impossible to use as an interconnect material as a result. Plus, copper was considered a horrible contaminant to be kept out of the fab at all costs. Even today, if you get a wafer in one of those plastic single-wafer containers, it will have a stripe of orange tape on it if it has copper on the wafer, meaning that it should not be let anywhere near the FEOL. IBM developed the process that came to be known as dual-damascene. The name damascene comes from a technique making jewelry, where one metal (typically gold) is inlaid into another (typically steel or something black). The semiconductor approach is similar. Instead of putting down the metal and etching it, the oxide trenches are formed and then a thick coat of copper is put down over the whole wafer. The excess copper on top (the overburden) is then removed by CMP (chemical mechanical polishing) leaving just the copper in the trenches. Also, it leaves a planarized wafer ready for the next level of vias and interconnect. To further add to the complexity, copper diffuses into the various materials and so has to be surrounded by a barrier substance, such as cobalt or tantalum compounds. The "dual" in dual-damascene refers to the fact that usually two layers are filled at once, the interconnect and the centers of the vias in the layer underneath, which already have barrier metal liners in place so that the copper doesn't get to touch the surrounding oxide. One challenge with copper interconnect going forward is that that barrier metal in the vias. The bottom of each via has a layer of barrier metal, an unwanted byproduct of lining the sides of the hole, that all the current has to flow through, and also means that, as dimensions go down, the copper core running through the middle of the via, is getting smaller and smaller. The via is starting to be mostly higher resistance barrier metal. Possibly in the future, Ruthenium might be used which has lower resistance and other good properties, and could just be a plug. Most of the problems with scaling interconnect seem to be to do with liners in vias, not so much with the interconnect itself. For more perspective on this, see my post from last year IEDM: Coventor Panel on BEOL Challenges . Sign up for Sunday Brunch, the weekly Breakfast Bytes email.Image may be NSFW.
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