A few weeks ago I wrote a blog about face recognition . Coincidentally, face recognition was front page news earlier this week, with the announcement that it would serve as another authentication option to validate Aadhar cards (a unique ID number issued to all residents of India). So, besides the two existing biometric verifications - fingerprint authentication and iris authentication - face recognition too will be available from July 1, 2018, according to the Unique Identification Authority of India (UIDAI), the government agency that issues Aadhar IDs. So it was timely that the Tensilica Hackathon event was held as part of the VLSI & Embedded Design Conference in Pune earlier this month. This was a first of its kind event for Cadence worldwide. It was a competition to design a performance and power-efficient DSP for face recognition. Every human face has about 80 nodal points and some of these, measured by software, include the width of the nose, distance between the eyes, the depth of the eye sockets and length of the jaw line. These points are measured creating a numerical code, called a faceprint, representing the face in the database. Hackers had to design an optimized digital signal processor (DSP) processor for face detection using the Tensilica Xtensa processor architecture. The contest was open to engineering students across India. Ten teams comprising of two or three students each participated, mainly from colleges in Maharashtra since the event was taking place in Pune. A three-hour tutorial on the Tensilica Xtensa processor provided a good base for the students to understand the technology, and the two-hour lab session that followed gave the students a chance to wet their feet before plunging into the actual competition. The Hackathon, which went on for a full 24 hours, started once the lab session was completed, and both students and Cadence R&D engineers worked through the night to solve the problem. The winning criteria for the Hackathon challenge was to perform face detection for a given image in least number of DSP processor clock cycles. Finally, at the end of 24 grueling hours, “Team VIT!E” (I think it's pronounced as “Vit-ee”) from Vishwakarma Institute of Technology, Pune, were judged the winners. The last few hours were very tense, with the top five positions constantly changing based on timing and closure goals. It wasn’t all hard work, though. A welcome break came at 8.15pm, when a local band, Ujaan, re-energized the participants with their superbly rendered classic Bollywood hits. Students thoroughly enjoyed the break and came back to work as fresh as if it was the beginning of the day! The participants had nothing but praise for the Hackathon, and indeed the Tensilica R&D team had gone to a lot of trouble to take care of details big and small to make sure the event went smoothly. Even after working for 24 hours, none of the teams lost steam or threw in the towel. Congratulations to Team VIT!E and VIT Pune on their noteworthy win! Here's a picture of all the teams and organizers after it was all over.![]()
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