As discussed in the previous installment of this blog, a new class of atomic transactions was introduced in the AMBA® 5 ACE/AXI specification to make operations at the remote locations more streamlined and efficient. We have considered an example of AtomicStore transaction with ADD operation and discussed why it was more efficient than relying on the older semaphore-like exclusive operations. In this installment of the blog we will take a broader look at all atomic transactions and review the changes in signaling. To begin with, there are four (4) atomic transactions: AtomicStore AtomicLoad AtomicSwap AtomicCompare The first two transactions (AtomicStore and AtomicLoad) have eight (8) possible operations associated with them. These operations include Add, Bit Clear, Exclusive OR, and others. While AtomicStore provides response without data, all other transactions provide response with return of the original data from the remote location. Let’s consider the following use cases: If a CPU (Master) wants to unconditionally swap original data at a memory location with the new data, it relies on AtomicSwap transaction. In it, it provides a single data value which is the swap value. When target receives transaction, it unconditionally overrides the old data with the newly supplied one, and sends the original data back to master. Sweet and simple! But what happens if master does not want to blindly swap the data? What if it wants to do so only if data at the remote location matches a certain value expected by the master to reside there? In such a case, it relies on AtomicCompare transaction in which the master provides two data values – compare value and swap value. Upon receiving AtomicCompare, target compares the original value at the addressed location with compare value supplied with transaction, and only if they match, overrides the old data with the newly supplied swap value. As you can see, trying to achieve the same result with the exclusive transactions would require much more effort. In order to support new atomic transactions, the AMBA 5 ACE/AXI specification introduced an additional 6-bit wide AWATOP signal depicted below. Obviously, the AMBA 5 ACE/AXI specification improvements are not limited to the new class of atomic transactions. We will explore other improvements in the next installments of the blog.![]()
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