I started Breakfast Bytes on 8th October 2015, my first day back at Cadence. The very first (real) post was Cadence and imec Announce World's First 5nm Tapeout . I had to find out what I could about the test-chip, write it up, and publish, all in an afternoon. Since it was literally my first day, I had had to spend the morning in HR being assimilated, meaning that I missed the briefing calls that we did jointly with imec. By the time I got handed the press release after lunch, it was already mid-evening in Belgium, where imec is located. 3nm Test Chip At the end of February, Cadence and imec announced tapeout of the next generation test chip, this time at 3nm. The design used a "common industry 64-bit CPU" for the test chip, built with a custom 3nm standard cell library. The design was done using Genus synthesis and Innovus physical design. The tightest metal routing pitch was 21nm (as a guide to how aggressive this is, 80nm is the limit for single patterned 193nm lithography). Like the earlier 5nm test chip, both EUV and 193i multi-patterning were used to investigate PPA comparisons under both patterning assumptions. At 3nm, the big interconnect challenges are variation, and resistance (especially in the contacts/vias). For more information on this (not specifically related to this test chip), see my post IEDM Short Course: After 5nm from a couple of months ago. One aim of the test chip is to measure (and thus improve) variation. EUV at 3nm needs to be double-patterned, since the wavelength of EUV "light" is 13.5nm. It can also serve as a vehicle to experiment with new via and contact materials, such as cobalt and ruthenium. Design Technology Co-Optimization For most of the last few decades, Moore's Law had proceeded by scaling the process, then passing the design rules to the designers who would create the libraries. But we have reached the stage where just scaling the process alone is not enough. The standard cell libraries need to be more aggressively reduced in size by using fewer tracks. To enable this, additional process features can be added, which are not directly scaling. For example, contact-over-active-gate. One particular optimization is the addition of supervias to the MEOL. A supervia is one that goes up more than one level (without requiring a run of metal on the intermediate level, that runs into the minimum area requirement). Contact over active gate (COAG) is another big win, removing the need to have a separate gate contact away from the actual gate. Intel's 10nm process (which is really the same generation as what the foundries call 7nm) has it, as they announced at IEDM in December. I expect 5/3nm processes to all have it, and perhaps some second generation 7nm ones. It is not just the interaction of process and cell design, the way that place & route interacts is also important. For example, under some circumstances, leaving empty metal tracks through cells can result in smaller routed area, even though the space taken by the empty metal track makes the cell bigger. The increase in cell size is more than compensated by the improved routing efficiency. EUV Insertion All the foundries seem to be planning on EUV insertion during 7nm. Most have announced that the initial 7nm will be conventional lithography, with ability to switch in EUV without any change to design rules. It is expected that then a second version of 7nm will be introduced that assumes EUV and has more aggressive design rules on some layers as a result (and can't be manufactured with immersion lithography). Everyone is assuming that 5nm will be EUV, although there are still issues with defects at 5nm so it is not completely ready yet. However, EUV has made amazing advances in the last couple of years (I was a skeptic, I admit) and so it looks to me like the kind of problem that will be solved in the years that are available. Research is happening into the next technology, known as high-NA EUV (NA stands for numerical aperture, one of the measures of goodness of a lithography system). EUV steppers are already enormous, but high-NA EUV will require a lot more vertical space with the machines being two stories high. 1.5nm What might we see at the next node, at 1.5nm? Work hasn't really started so most speculation is still largely guesswork. Complementary FET (CFET) looks attractive, where the P and N transistors are stacked on top of each other. This is a one-time saving, but obviously reduces the area that the transistors require significantly. However, there is a possibility that the reduction in area from stacking the transistors might be reduced by the difficulty of handling the routing since there are now two transistors that need to be hooked up in what used to be the space for one. As the example of leaving some empty tracks in large standard cells shows, sometimes routing is counterintuitive. FinFET is probably going to be replaced with horizontal silicon nanowires, also known as GAA (gate-all-around). Actually, nanosheet, where the wires are not circular but flattened. The big advantage is that GAA can provide the same drive at a lower voltage, with the corresponding power savings. Buried power rails are likely. Already at 7/5/3nm, a lot of the routing resources are consumed by the need for regular power stripes every few tracks, and the number of routing tracks between power stripes goes down with each process generation. Being able to provide power without using a lot of routing resource is a big win. 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