CDNLive is a user conference, and verification is one of the largest categories of content with multiple tracks covering multiple days. Portable stimulus is one of the hottest new areas in verification, and continues to be popular in all venues. At last year’s CDNLive we heard from Sanjay Gupta, Qualcomm Technologies Inc, on their use of Perspec for verifying every mobile SoC . After the long lines at DVCon 2018 to see demos of Perspec PSS (v1.0 draft specification), we’re providing even more sessions at this year’s CDNLive. You can also learn more about the Accellera standardization process, expected to produce a published standard later this year. Here is an interview of Sharon Rosenberg , discussing the status of the standardization activity, and what’s important for the industry when adopting portable stimulus. Three Portable Stimulus Sessions IPB104 (Cadence) Accelerating SoC Verification Closure with Perspec Portable Stimulus and the Xcelium, Palladium, and Protium Platforms Speaker: Swami Venkatesan, Sr Solution Architect, Cadence Tuesday, April 10, 3:25pm - 4:05pm, Room 206 Session Description : SoC Verification closure requires coverage of system use cases. These use cases defined with a portable stimulus language allows users to execute them on Xcelium simulator, Palladium Emulator and Protium FPGA platforms. This presentation details use of Perspec coverage to cover important SoC coverage items, including coverage of action sequences, event density coverage, low power coverage, concurrency coverage and temporal coverage of actions. Such a portable coverage analysis gives useful insight to system level interactions occurring in a SoC. VER201 (TVS) Delivering on the Promises of Portable Stimulus Speaker: Mike Bartley, CEO, Test and Verification Solutions, and Swami Venkatesan, Sr Solution Architect, Cadence Wednesday, April 11, 9:30am - 10:10am, Room 207 Session Description : As products become more complex and market windows continue to shrink, efficiency in product development can translate directly into competitive advantage. We understand what improves efficiency in verification: abstraction and reuse; but how to achieve that? Accellera are looking to address this through the Portable Stimulus Specification (PSS). The reuse revolution started in design IP and has contributed hugely to design efficiency. Verification IP soon followed in the form of eVC and latterly UVC but these miss the main point: the currency of verification is stimulus (and checkers, of course). Verification has to deal with multiple dimensions of reuse: Hierarchy (block, subsystem, SoC, system) Platform (simulation, emulation, FPGA prototype, Silicon) Project (reuse from one project to the next) In this paper we look at how PSS and Perspec delivers real reuse along all of these through abstraction. VER202 (Arm) Integration and Verification of PCI Express Gen4 Root Complex IP into an Arm-Based Server SoC Application Speakers: Sridhar Valluru, Sr Product Manager, Arm, and Swami Venkatesan, Sr Solution Architect, Cadence Wednesday, April 11, 10:15am - 10:55am, Room 207 Session Description : Now that more IP is available that supports the SMMUv3 and GICv3 architecture specifications from ARM, the enhanced capabilities of the fourth generation of the PCI Express standard can be realized in ARM SoCs. There are many architecture, integration, and verification challenges that must be overcome to succeed. This presentation covers several of the key issues in such projects, and highlights solutions that Arm and Cadence are employing to overcome them.![]()
↧