The release of PCIe 4.0 rev 1.0 in October 2017 was anticlimactic after the announcement of PCIe 5.0 rev 0.3 at last year’s PCI-SIG DevCon. Fast forward, this year’s DevCon has kicked off and the SIG is clearly demonstrating its commitment to the accelerated development of PCIe 5.0. PCIe 5.0 rev 0.7 is published and already out for membership review as of May. The big-ticket item is, of course, support for 32GT/s. Table 1: PCI Express Bandwidth Generation Raw Bit Rate Link BW BW/Lane/Way Total BW x16 PCIe 1.x 2.5GT/s 2Gb/s 250MB/s 8GB/s PCIe 2.x 5.0GT/s 4Gb/s 500MB/s 16GB/s PCIe 3.x 8.0GT/s 8Gb/s ~ 1GB.s ~32GB/s PCIe 4.x 16.0GT/s 16Gb/s ~2GB/s ~64GB/s PCIe 5.x 32.0GT/s 32GB/s ~ 4G ~128GB/s The higher bandwidth will be welcomed by high-performance applications like AI, machine learning, storage, and high-performance networks to name a few. There are minimal electrical changes projected and the industry already has PHYs running at 28GHz/56GHz. Cadence also demonstrated a multi-protocol PHY showcasing support for 32Gbps in 7nm. Figure 1: 32Gbps TX eye-diagram with PRBS pattern Cadence verification IP built on top of its solid reputation by being first to market with support of PCIe 5.0 rev 0.3 at 32.0GT/s in November 2017 . We have started enabling early adopters with PCIe 5.0 rev 0.7 controller and verification IP, to aggressively start testing at the higher bandwidth. But will Gen 5.0 spec development drag like Gen 4.0? Unlikely. Protocol wise, a substantial amount of work was done for PCIe 4.0 that PCIe 5.0 is piggybacking off of, and areas such as tags and flow control will remain untouched. However, there are still areas that will pose interesting challenges for the design and verification teams. The equalization procedure is getting a substantial overhaul. First introduced in PCIe 3.0, dynamic equalization is non-trivial but a necessary evil to deal with the signal integrity issues amplified at higher speeds in the absence of changes to the transmission path. For PCIe 5.0, the upgrade to lower-loss materials from FR4 counters the increasing channel loss. The upgrade also allows designers to consider bypassing the equalization procedure to minimize latency bring up. Rather than performing at equalization at lower data rates (Gen 1.0 to Gen 3.0 to Gen 4.0 to Gen 5.0) the link can go directly to the highest supported data rate or directly from Gen 2.0 to Gen 5.0. From a verification point of view, link equalization poses a major challenge for all three flavors. Verification teams need to ensure that the LTSSM is transitioning correctly for the scenarios. Adding the bypass mechanisms should not break the legacy behavior, otherwise the link cannot be trained to Gen 3.0 and above. The highly configurable Cadence PCIe VIP fully models the LTSSM and relevant specification define registers. With over 350 registers, 90+ checkers, and fully configurable timing parameters, the user can fully exercise transmitter/receiver presets/preset hints, coefficients, etc., and have confidence that their DUT performs the equalization correctly. New for PCIe 5.0 is the option to negotiate the support of alternate protocols during configuration through the exchange of modified TS1/TS2 ordered sets with 8b/10b encoding. This allows non-PCIe protocols to use the PCIe PHY layer. This complements the changes seen in the PIPE 5.0 SerDes Architecture, which moves the protocol-specific complexities from the PHY design to the MAC. The increased frequency also translates into an increased probability of errors. While precoding will not change the probability of encountering an error on the serial line, it does break down burst errors. Precoding is a feature that is being introduced for 32GT/s, which reduces the chance of a big string of 0s that will break the CRC mechanism. When precoding is enabled at the transmitter, it only acts upon scrambled bits. This poses an additional level of complexity for both receiver and transmitters Overall, the SIG is holding to its accelerated spec development. The buzz this year has switched from “When will PCIe X be released” to “When will be PCIe 5.0 be adopted”. With its many years of leadership in the verification of PCIe systems, Cadence is acting upon the new developments quickly and ensuring they’re ready to address customer needs when they pull the trigger.![]()
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