Another year, and another DAC. As usual, the proceedings kicked off on Sunday night with the welcome reception, and that went straight on to the Heart of Technology (HOT) party, raising money for the Gary Smith Memorial Scholarship at SJSU. Lori Kate was there with their son. Jim Hogan's Vista Roads band provided the music. This all took place in the 3rd floor lobby of Moscone West, a new location for DAC. Cloud and Machine Learning After attending some presentations and looking around the exhibit hall, it is obvious that the two big themes this year are cloud and machine learning. Cadence announced our cloud offering this morning, and you can read my post about that Cadence Cloud . I won't repeat any of that here In Cooley's Troublemaker Panel (see below) Cadence's CEO Emeritus Joe Costello said: I’ve been away from EDA for a while, but it’s obvious that everything is going to be in the cloud 5 years from now so for sure it’s going to happen this time. One big change in the exhibit hall is Infrastructure Alley. There is also a second pavilion there, the Cloud Pavilion. AWS Keynote The opening keynote was given by Sarah Cooper of Amazon Web Services, where she is GM of IoT Analytics and Applications. The title was Living Products: Building Connected Devices that Learn and Evolve . She started off pointing out that everything happens faster today. It took 50 years to get a telephone into 70% of US homes, but it only took smartphones 7 years. She'd just sold her car, which was 8 years old, and had a 6-CD player in it, something that is essentially obsolete. In fact, when I bought my current car, a Mini, I was told it was the last year they were putting a CD player in at all. Consumer tastes change faster and faster. Furthermore, younger consumers are less attached to "things" and experiences trump products. Connected products require innovation after installation, and personalization requires machines that learn. As everyone says, "data is the new oil". Sarah pointed out that it is the new oil in a less obvious sense. Just as the oil went through several processing steps before you put it in your car, so the data will be processed many times before it is useful. Another change that this sort of adaptable product can lead to is building "things" out of existing products. An example would be building a baby monitor out of existing devices such as cameras, voice-recognition and so on. It's not a big problem technically but it is a business problem when the devices are from different manufacturers. Sarah talked about smart lighting in airports and how the funding can be justified entirely by using the lights to track wheelchairs. That's before moving on to detect people, see traffic flow and other things. Interestingly, Joe Costello in his keynote a couple of years ago was also told by hospitals that wheelchairs are a huge problem for them since you generally can't be discharged except in a wheelchair. See my post DAC Opens with an Enlightened Keynote . The takeway is that if you want to future-proof systems (remember, they are only going to take 7 years or less to get into 70% of homes) then you need devices that learn how they are being used and update themselves. Future proof products with learning systems. Handel Jones In the DAC Pavilion, Handel Jones kicked off the first day with his look at the future. The key takeway is that there is a major shortage of design capacity. Handel reckons there are 240,000 design engineers worldwide, and thinks we are short about 200,000. Since it takes maybe 10 years to become a designer for a leading edge node, that is not a problem that can be fixed. Handel spends a lot of time in China and he sees it as the biggest market for datacenters, partly because the population is 1.3B compared to 330M in the US. But it is also the clear leader in 5G in terms of technology, tests are being installed. They expect 1B 5G users in 2015-27. 5G is needed for automated driving, and China is assuming their coverage will be really good, like for 4G (in all my time in China, I've never had no signal—not in the country, in subway tunnels, basement levels in shopping malls etc). Handel sees growth through 2027 with a possible downturn in 2020 if memory prices weaken. The leader in process technology today is Samsung, slightly ahead of TSMC, and Intel a bit behind that. But it is easy to miss that there is a big market in mature technologies like 3130um, 180um. But there is coming excess capacity at 28nmm, mostly due to overinvestment in China. He sees EDA growing strongly (the slide shows only IP revenue from EDA companies, and excludes Arm and Qualcomm). Design starts are fairly flat. The scale of a leading edge design is huge. In 5nm there are about 12B transistors on an 80mm2 die. There doesn't seem to be cost reduction going to these very advanced nodes. There is a big power saving, and a big gain from integration where you no longer have to go off-chip. Handel had his usual criticism of the EDA industry, that the value of EDA is low compared to the impact on the semiconductor industry. Or, putting it more brutally: If you are an EDA vendor, why do you get so little money? Will it change? We don’t think it will. Handel's proposed solution to EDA not getting its fare share and the shortage of engineers is that we (I'm not quite sure who "we" actually is) should build mega-design centers, with huge supercomputer capacity and AI to support the EDA tools and improve productivity. The analogy is with a foundry, where it takes about $15B to put in place 50K wpm capacity, another $3-5B for process development. And there are only 3 companies globally. He sees a parallel with design. To us, every company investing in the same stuff just can't go on. There are only 10 companies globally doing 5nm designs. There will be pushback from the people that currently own the IP (things like 5G modems) but Handel sees this as feasible. I'm not so sure, since IP like a 5G modem is far from a commodity. Looking further forward to 3nm and 2nm, he sees the process cadence slowing down to 4 years, maybe 5 years. Even if the transistor scales, the MEOL and BEOL need to scale. Interconnect parasitics are the main thing that drives performance. If you don't scale the BEOL you don't get improvements in either performance or density. Cadence Verification Lunch Every day during DAC, Cadence has a lunch. On Monday it is always verification. Everyone gets to eat lunch (well, I get to take notes) while the panel on stage discusses verification. This year the topic was Smarter and Faster Verification in the Era of Machine Learning, AI, and Big Data Analytics. The panel was moderated by Ann Steffora Mutschler of Semiconductor Engineering. It consisted of: Jim Hogan, Vista Ventures David Lacey, HP Enterprise (HPE) Shigeo Oshima, of Toshiba Memory Corporation Paul Cunningham, Cadence's head of verification I'll try and give you a little color on each person's opening statement and then some of the more interesting points made during the Q&A. Jeff Oshima of TMC Note: TMC is Toshiba Memory Corporation, not to be confused with TSMC, Taiwan Semiconductor Manufacturing Corporation. Shigeo (Jeff) Oshima went first and explained that his company is maybe not what you think it is. Toshiba Memory Corporation (TMC) is actually now completely independent from Toshiba. It will move out from Toshiba's headquarters and into their own building at the start of next year, and in spring next year should have a new (non-Toshiba) name. They have adopted an agile design methodology with frequently changed requirements from the market, causing many design and verification iterations. They design two main chips: vertical NAND flash (obviously memory) and the controller (a mainstream digital SoC), which handles the data movement but also things like wear leveling (flash memory has a limited number of write cycles so the writes need to be moved around). The controller is 16nm, they don't need anything to that 7nm offers. They have been using more formal verification, which has reduced the number of escaped bugs. In TMC, verification is a big issue since its cost increases exponentially if there is no progress in new technology. So innovation is required. Paul Cunningham of Cadence Paul started by drawing attention to the fact that you can't do perfect verification: Verification is an intractable problem, every time we double the size of the chip we square the state space and so verification is never done One big issue is that there are different engines and different hardware on which they can run. Traditional simulation can run on x86 (Xeon), or Arm, or FPGA, or custom hardware aka Palladium. Which engines do you use in which cases? "It doesn't really feel efficient right now, we are burning millions of cycles without increasing coverage, covering the same things multiple times. David Lacey of HPE David said there are three areas he is focused on: making our engineers more productive, they are our most expensive resource we spend a lot on tools, so how do we use them to get better value from them managers want more predictability, so how do we deliver that The first thing is to collect data, and to look at all the technologies available. It is not just having the feature but also having a smart way to consume that feature so that it enhances the engineer's productivity and is not a distraction. Jim Hogan of Vista Ventures My business is investing in companies so at any point we have about 14, 15 companies. About half are semiconductor, about 3 are EDA. It’s often the case that you can be too early to market and I’ve suffered many times with that. What I like about verification is there is a big sea change with cloud coming in. We have AWS and Google here for the first time. There will be hardware changes and business model changes. I don’t know who the winners will be. The verification problem is intractable, as Paul said, it just gets bigger and bigger. But from an investment point of view I love that. I did a course on formal years ago, and my professor told me that the market would be huge. They just didn't tell me when. Now here we are 40 years later, and it is finally here. Automotive safety means we need to be able to say when enough verification is enough, we have to formalize that. Discussion One thing that came up a lot in the discussion was being smarter about deciding when to use the various engines. It is easy to continue running all the simulations and add formal. But that is not the idea. As Paul said, "if formal is working then you should be able to do less simulation." One challenge is that some engineers are not willing to try new approaches, formal in particular. Paul said that there are some simple things that show the value clearly with only small effort, such as reachability analysis that can show that no amount of simulation will ever get to a certain place. Reset sequences on a whole SoC are often easy with formal. There are also lots of static things you can check for such as power-domain crossing, level shifting and the like. This can reduce the number of testbenches needed. Another challenge is that coverage needs to be taken up a level. Coverage at the statement level is useful, but it doesn't tie in well to different approaches and it is too low level. Everyone agreed that we need to agree what coverage means since that's part of the way we can tell when we are done. Obviously, combining coverage from all the engines is a first step, but Cadence wants to do something more transformational than that. When you are running 50,000 IP regressions, could you get the same confidence from just 10% of them. How do you pick them? Ann wrapped up by asking each panelist to give two sentences on what is needed in the future. But some only needed a couple of words: Jim: Intelligent workbench David: for me and our team, how do we make our investments more valuable and become more predictable Oshima-san: flash memory and SoC controller is all I work with Paul: smart coverage Cooley Later, it was Cooley's Troublemaker Panel. It was a standing room only crowd, with many people unable to even get in the door. This year the panelists were: Joe Sawicki - Mentor Siemens Anirudh Devgan - Cadence Dean Drako - IC Manage Mo Faisal - Movellus Joe Costello - Montana John Cooley, as always was the master-of-ceremonies or the herder-of-cats. I'll pick a few questions and answers, the whole panel lasted an hour so is too much to put here in full. Cooley: "So Joe Sawicki, are you next Wally Rhines?" he opened with. Joe wasn't going to take that bait. "Wally's job is changing, but how do you replace Wally? His model is Morris Chang." Cooley: "Anirudh, you just announced you are going whole hog into the cloud. Synopsys did it in 2000 and 2011 with DesignSphere. Why is this going to work now?" You have to look at cloud holistically, and at one customer about 60% of use was verification, 20% was circuit simulation, 20% implementation. That’s not how they would spend their EDA money but 80% are the batch simulation task. So there is demand for either complete outsourcing or peak usage. But lots have to come together. Need good infrastructure. We’ve been working with Google, AWS and Microsoft to make sure infrastructure is good. But need security too. HR systems, finance systems, people have established that trust. So ecosystem is important too, so we worked with Arm and TSMC and they ran security audits. 3rd piece is that the tools have to be able to run in the cloud. We have EDAcard from Joe’s days. So infrastructure, security and ecosystem, tools and biz model and we have a credible solution and we’ll see how the customers accept it. Cooley: Joe Sawicki, why did you only go half-hog and just put Veloce in the cloud? Joe: We haven't announced everything. Does anyone here really need me to announce Calibre in the cloud? I was at the front so couldn't see but apparently the only person who put a hand up was a Mentor employee. Joe Costello talked about the merger of Montana with Metrics, announced the day before: I’ve been away from EDA for a while, but it’s obvious that everything is going to be in the cloud 5 years from now so for sure it’s going to happen. That’s why I though Metrics was on the right path. We at Montana needed a new front-end capability to go with our back end. Cooley: You talked about Montana 5 years ago? What is Montana? Joe Costello: We build a new architecture for a processor that runs SystemVerilog directly. That is that it’s a *** of a problem and we started with the wrong people, then a different group, and finally got a team that could put it all together. Cooley: Joe Sawicki, why did Veloce lose to Zebu at Intel? Joe: I'm not saying anything about any particular accounts, but we were two years late on the hardware with Stratus, we’ve recovered some of that share. We were in the market with a poor chip for a couple of years. “We were late on a chip, that hurts.” Cooley: "Anirudh and Sawicki, is seascape from ANSYS John Lee’s company, a big deal?. Did you regret not acquiring them? Sawicki: Seascape is an interesting approach for parallelization. There is turmoil in the market. Cadence has done their announcement, we haven’t made ours yet (cough...“just clearing my throat”). Cooley closed with the DAC drama. Thiis that the ESD Alliance has marged into SEMI. There will be an EDA Pavilion at SEMICON next year (not the one in a few weeks). But DAC is not ESD Alliance, so will everyone really go to DAC in Vegas in June next year, and then SEMICON West in July in San Francisco. John Cooley asked everyone explicitly if they would be at DAC next year: Anirudh, will Cadence be at DAC. Anirudh: yes, we want a vibrant DAC. Will you be at SEMICON West? We don’t just go to DAC, we go to a couple of dozen shows. Also we are moving more to the system space. Sawicki, will Mentor be at DAC? Joe: we will be at DAC next year. We have been a SEMICON West for years focused on manufacturing with a small booth. Dean: will you be at DAC? Yes. We will be at the EDA Pavilion in SEMICON West next year too. Mo: will you be at DAC? We will go where our customers go. Sign up to get the weekly Breakfast Bytes email:![]()
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