Every year, the Monday before SEMICON West, imec hosts ITF US, the US version of the imec Technology Forum. The big one is held in Brussels in May, and lasts for two days with an amazing dinner on the evening between. The two I have attended had dinner in a beautiful old shopping arcade, and in the Magritte Museum. But the US version is just an afternoon long (although they do provide lunch). Since imec is in Belgium, and they were playing on Friday in the World Cup, it is great to kick off (see what I did there?) this post with the news that giant-killers Belgium eliminated favorite Brazil from the World Cup. Brazil scored twice, and Belgium only once...but unfortunately, the first goal of the match was an own goal by Brazil. Talking of the World Cup, since I'm English, it was great to see them eliminate Colombia on penalties. Not just because they go through, but England have a jinx on World Cup penalty shootouts—until Tuesday, they had a 100% record of losing them and being eliminated. Then on Saturday England beat Sweden to reach the semifinal for the first time since 1990 (but without needing penalties). Unfortunately, since the ITF on Monday, Belgium were beaten by France as I write this on Tuesday. I recently visited imec so I wondered whether I'd learn much new, but I needn't have worried. There was a little overlap on process roadmaps and EUV, but most of what was presented I had never seen before. For the posts about my trip to imec, see: If It's Tuesday This Must Be Belgium. My First Visit to imec Imec Roadmap Imec on EUV. Are We There Yet? Imec Technology Forum US I won't try and write about everything that was covered in the afternoon. But I will give you the program so that you can see the range of topics covered: Luc van den Hove, imec's CEO, New Perspectives Creating Radical Innovation Scott DeBoer, Micron's EVP of Technology Development, New Memory Frontiers: Enabling the Data Economy An Steegen, imec's EVP of Technology and Systems, Technology for a Tomorrow's World Dan Mocuta, imec's Director of Logic Device and Integration, Nanosheets, CFETs: A Perspective on Logic Scaling and Beyond Greg McIntyre, imec's Director of Advanced Patterning, EUV Stochastics: Challenges and Solutions Antun Domic, Synopsys' CTO, Innovation Runs at a Scarily Fast Pace Jan Van Houdt, Distinguished MTS, Ferroelectric & Exploratory Memory at imec, The Return of Ferroelectrics Nadine Collaert, Distinguished MTS at imec RF Beyond the Speed and Power Limits of CMOS Zsolt Tokei, imec's Program Director Nano-interconnect, New Conductors - Reality or not? Philippe Absil,imec's Director 3D & Optical I/O Technologies, Scaling the Bandwidth with Silicon Photonics When I think of imec, I think primarily of the process roadmap stuff. And there was plenty f that with An Steegen's overview, a deep dive into EUV, a look at the implications of CFETs (stacking the N and P transistors on top of each other), ferroelectrics, next-generation connector materials and more. I will cover some of the other presentations in a couple of posts in the coming weeks. Luc van den Hove Luc kicked off the afternoon with a big picture overview of some of the work that imec is doing. Since this was SEMICON, the rest of the day was completely focused on semiconductor. But actually imec does a lot of other things such as medical. There is usually some electronic angle too, to go along with the technology in the neighboring space, such as neurons on a chip used to help understand dementia and other things. Other things that Luc discussed, that imec is working on: haptic feedback new display technology fast eye-tracking glasses using electro-oculography EOG, see on right early detection of neuro-degenerative diseases machine learning in battery powered devices extremely low power neural networks electric cars batteries memory technologies such as MRAM and RRAM quantum computing reading and writing DNA as a storage technique micro-fluidics Scott DeBoer Micron's Scott DeBoer gave one of the invited keynotes, New Memory Frontiers: Enabling the Data Economy . He started by pointing out that 20,000 billion GB of data were created in 2017. If you think that is a pretty odd unit of measurement, he said it comes from talking to the financial community, who don't really understand numbers bigger than a billion so zetabytes just go over their head. Micron is involved in storing a lot of that data, either temporarily or permanenty. They are the only company with a complete porfolio of memory technologies: DRAM, 3D NAND, NOR, 3D Xpoint, and some emerging technologies. The DRAM market was largely built up around enabling personal computer systems, with a uniform spec. But DRAM today has to serve a lot of different requriements. For example, datacenters have specific high-performance needs and very low defect levels, but a constrained temperature region. Whereas, at the other end of the scale, in automotive the temperature range is extended and reliability is key...but then in the infotainment systems the requirements are different again. Mobile is almost all about power and extending battery life. In the past, as with logic, it was all about scaling. But different types of innovation have been required. Two that Scott talked about were: CUA, or CMOS-under-array. The periphery of a normal memory die has digital logic to handle interfacing to the outside world and so on. One way to cost-reduce the memory and improve performance is to move the logic to a separate die and put it underneath the bit array, as in the diagram on the right 3D NAND array stacking. Instead of attempting to build a 64 layer 3D NAND, two 32 layer ones are built and then the two wafers are stacked to create a 64 layer with less aggressive manufacturing requirements. The big challenge in 3D NAND is the deep etch that has to create a hole with an extreme aspect ratio that goes down through the entire stack of layers. For DRAM, there are challenges but Scott says the technology roadmaps do extend several nodes. The feature size reduction is slowing. The roadmap does not require EUV. But after a few nodes there are big challenges and a chance that it might not continue to scale. But as Scott pointed out: I've said I can only see 3 more nodes many times before in my career. But every time we cae up with something. There are no memory technologies as high performance and scalable as DRAM. We need a new memory in that corner. For 3D NAND, Micron are going up to 96 layers in 2018, stacking two 48 layer die on top of each other, 48+48 and going up from 3 bits per cell to 4 bits per cell. 3D XPOINT is storage class memory. Scott described it as "the only emerging memory technology to actually emerge." One interesting statistic I'd not heard before: the cost of the memory in a phone is now approaching 2X the cost of the CPU. The diagram above shows the breakdown for the iPhone 8. The memory is quarter of the cost of the entire phone, including everything (case, battery, processor etc) not just the chips. Cost of memory is now approaching 2X that of the CPU. Phone refresh cycle drives innovation. See pic chart pic. So memory forms a hierarchy from the CPU. The grey boxes on the left are the cache memories, typically static RAM on the SoC or in the same package. The colored boxes go from DRAM through NVM (which is 3D Xpoint, although to be honest that stage in the memory hierarchy hasn't really been adopted) to SSD (solid state disks) and HDD (rotating disks). Sign up for Sunday Brunch, the weekly Breakfast Bytes email.![]()
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